CS355 Sylabus

Executing an ALU instruction: Part 2 - a register and a constant

We now examine in detail how the basic pipeline CPU execute instructions with constants as second operand.

ALU instructions with a constant as source operand 2
- Example: add r1,r2,#3 (R1 := R2 + 3)
- The instruction is encoded as follows:
```
            Dest Reg           OpCode   I   Src Reg1    Src Reg2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+  

  = 8  83 (decimal value of each byte)
```
  - Notice the Immediate mode bit (highlighted) is set to 1 to indicate that the SRC2 field contains a constant number
Slideshow:

(Cycle 1: fetch ALU instruction in ID stage)

(Start of cycle 2: ID stage fetch operands)

(End of cycle 2: operand fetched, instruction advances)

(Start of cycle 3: EX stage obtain operands)

(End of cycle 3: results stored in ALUo (and DMAR) registers, instruction advances)

(Start of cylce 4: MEM stage execute LD/ST/Branch instruction)

(End of cycle 4: MEM stage did nothing, instruction advances)

(Start of cylce 5: WB update destination register, instruction advances)

(End of cylce 5: destination register updated, instruction discarded)

❮ ❯
Step 1: Fetch
- At start of the CPU cycle, the IF stage sends out PC
- At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (add r1,r2,#3)
- The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)
Step 2: Decode (fetch operands)
- At start of the CPU cycle, the ID stage sends out selection signal that selects value from R2 (and also R3 !!! - R3 is fetched but will not be used)
  The ID stage also extracts the constant (=3) stored inside the instruction "add r1,r2,#3"
- At end of the CPU cycle, A register is updated with R1, and IR1 register is updated with the value 0000000000000011 (= 3)
  Incidently, the B register is updated with R3 because the ID stage does not know which operand will be used.... You will see in the next step that there is no harm in fetching R3 into B.
  And ofcourse, D register is updated with R1 (but R1 will not also be used in this instruction).
- Also, at the end of the CPU cycle, the instruction (add r1,r2,#3) is moved into IR(EX) and a new instruction is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)
Step 3: Execute (compute)
- At start of the CPU cycle, the EX stage selects values from R2 in A register (and not PC1) and the value in register IR1 (= 3, and not the value R3 in the B register, because the Immediate mode bit = 1 !) for the ALU.
  It uses the ALU opcode (00 = ADD) to select the addition operation of the input values (R2 + 3)
- At end of the CPU cycle, ALUo and DMAR registers is updated with the value R2+3 !!!
  Also, SMDR register will be updated with the value R1 (but this value will not be used by the instruction - see next step).
  So you can see now that fetching R3 into the B register was harmless - the MUX will use the constant (=3) in IR1 to execute the instruction.
- Also, at the end of the CPU cycle, the instruction (add r1,r2,#3) is moved into IR(MEM) and a new instruction is fetched into IR(EX):
- The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)
Step 4: Memory Access (load/store) or Branch instruction execution
- Because the MEM stage of the basic pipelined CPU is used to execute memory access instructions (= load/store) and branch instructions, and "add r1,r2,#3" is neither, there is no processing taken place in the MEM stage for this instruction.
- At end of the CPU cycle, ALUo1 registers is simply updated with the value R2+3
- At the end of the CPU cycle, the value R1 in SMDR register is discarded (SMDR register is only used in a STORE instruction - see later)
- Also, at the end of the CPU cycle, the instruction (add r1,r2,#3) is moved into IR(WB) and a new instruction is fetched into IR(MEM):
- The picture above depicts the content of the CPU at end of the 4rd CPU cycle (and the start of the 5th cycle)
Step 5: Update register
- At the start of the CPU cycle, the destination register (R1) is selected by the Dest field of the IR(WB) and the value in ALUo1 (= R2 + 3) is selected for output on the C-bus (because the instruction is an ADD)
- At end of the CPU cycle, the register R1 register is updated with the value R2+3
- Also, at the end of the CPU cycle, the instruction (add r1,r2,#3) is discarded and a new instruction is fetched into IR(WB)
- The picture above depicts the content of the CPU at end of the 5rd CPU cycle (and the start of the 6th cycle)

Example Program: (Demo above code)

/home/cs355001/demo/pipeline/1b-ALU-instr+with-const

Executes the following instructions:

10 65 // mov r1, #65 R1 = 00000000 01000001 18 4 // mov r2, #4 R2 = 00000000 00000100 26 24 // mov r3, #24 R3 = 00000000 00011000 34 2 // mov r4, #2 R4 = 00000000 00000010 42 8 // mov r5, #8 R5 = 00000000 00001000 58 3 // mov r7, #3 R7 = 00000000 00000011 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 8 83 // add r1,r2,#3 (R1=R2+3) R1 := 00000000 00000111