- Conditional branches is usually preceeded by a
COMPARE (actually a subtract instruction
that does not modify any register) instruction.
The COMPARE instruction would set the NZVC flags and the conditional branch instruction must decide whether the branch should be taken based on the setting of the NZVC flags.
- Consider the following program fragment with a conditional
branch instruction:
CMP R1, R2 Bcc Label ADD R2, R1, R2 ADD R3, R1, R3 ADD R4, R1, R4 ...
- The CMP is actually a subtract instruction,
but the Enable-C is not set (so no register
is update.
Although out toy CPU does not have a subtract instruction, for the sake of discussion, we just assume that the CPU does have one (and it is quite easy to expand the CPU with subtraction capability).
- The gist of the discussion is to show you how the CPU can
use the flag setting produced by the COMPARE instruction
in the BRANCH instruction
- Again, I will label the address of the branch instruction in memory with a red color in the figures below to highlight it....
Slideshow:
(Cycle 1: IF stage fetched the CMP instruction)
(Start of cycle 2:
IF stage fetches the conditional branch instruction,
ID stage fecthes operands for CMP)
(End of cycle 2: branch instruction fetched -
PC advances to next instruction,
ID stage fecthed operands for CMP,
all instruction advances)
(Start of cycle 3:
IF stage is fetching next instruction,
ID stage computes branch destination address !!,
EX stage compute N,Z,V,C flags)
(MIDDLE of cycle 3:
EX stage updated N,Z,V,C flags !!!
)
(End of cycle 3:
IF stage fetched next instruction,
ID stage updated PC with branch address
using N,Z,V,C flags of CMP instruction
(branch instruction has branched
on the correct condition !!!)
)
- At the start of the cycle, the CPU sends out value
PC which is the address of the COMPARE instruction.
- At the end of the cycle, the IR(ID) is updated with
the COMPARE instruction and
the PC is incremented to the address of the BRANCH instruction:
- At the start of the cycle, the CPU sends out value
PC which is the address
of th branch instruction "BRA Label"
- The value PC will also be sent
to the input of the PC1 register
- The COMPARE instruction in the ID stage will fetch
the values from register R1 and R2 for the A and B registers,
respectively:
- At the end of the cycle, the following registers (of interest)
are updated simultaneously: PC register with the value
PC+4,
PC1 register with the value PC and
IR(ID) with the "BRA Label" instruction,
A register with R1, and B register with R2.
- The picture above depicts the content of the CPU at end of the 2nd CPU cycle (and the start of the 3rd cycle)
- At the start of the cycle, the CPU sends out value
PC+4 which is the address
of th branch instruction "add r2, r1, r2"
- The adder circuit in the ID stage will add
the value PC in the PC1 register
and the offset in instruction register IR(ID) to form
the target address "Label".
- The NZVC flags has NOT been updated yet and
let's assume that the branch condition code
in the ID stage (the conditioncal branch)
will cause the SELECT circuitry in the ID stage
to select (PC+4) + 4
for the PC register in the IF stage.
- In the mean time, the EX stage is computing the subtraction of R1 and R2
and sending the new NCVZ flags to to PSR register:
- At the middle of the cycle, the PSR registers (and the NZVC flags)
are updated.
The NEW values of the NZVC flags will cause the
selection circuitry to recompute
the selection signal -
if the condition of the branch is satisfied,
the selection circuit will select the
PC+offset (= Label)
value:
- At the end of the cycle, the following registers (of interest)
are updated simultaneously: PC register with the value
Label
(= PC+offset),
IR(EX) with the "Bcc Label" instruction,
IR(ID) with the "add r2, r1, r2" instruction and
the ALUo register with R1-R2:
- Notice that the ALUo register dwhas the value R1-R2, but
the Enable-C bit in the COMPARE instruction is not set,
therefore, no register will be updated and the R1-R2 value
will be harmlessly disposed later...
- The picture above depicts the content of the CPU at end of the first
CPU cycle (and the start of the 2nd cycle)
- The CONDITIONAL BRANCH instruction has executed correct
- again with one instruction delay (no surprise here)
- The blue circuit
labeled
SEL in the
pipelined CPU is
used to
"evaluate" whether the
branch condition is
satisfied
- Without going into
details of the
flag setting
(will require me too explain too many details),
the following is the
flag settings
for the conditions used
in assembler programming
taught in CS255:
- Recall that the
conditional branch instruction is
encode
(by Aaron) as
follows:
Branch condition <-------------- branch offset -----------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | B | B | B | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ B B B Branch condition --------------------------------------------------------------- 0 0 0 Branch always 0 0 1 BEQ 0 1 0 BNE 0 1 1 BLT 1 0 0 BLE 1 0 1 BGT 1 1 0 BGE 1 1 1 not used
- The
Branch evaluation circuit
is constructed using
a decoder to
identify the
conditional branch condition and
additional combinatorial circuits
to detect the
true condition(s)
for each case/
- A partially completed
branch evaluation circuit is
as follows:
