- Consider the following program fragment with an unconditional
branch instruction:
BRA Label ADD R2, R1, R2 ADD R3, R1, R3 ADD R4, R1, R4 ...
- When the BRA Label instruction is fetched
by the CPU, the value of the program counter PC
must be equal to the address of this branch instruction
in memory.
- Since this memory address value (the address of the branch instruction in memory) will be used to compute the target branch address (by adding the offset to this address), I will label this value with a red color in the figures below....
Slideshow:
(Start of cycle 1: IF stage is fetching branch instruction)
(End of cycle 1: branch instruction fetch,
PC advances to next instruction)
(Start of cycle 2: IF stage is fetching next instruction,
ID stage computes branch destination address)
(End of cycle 2: IF stage fetch next instruction,
ID stage update PC with branch address
(branch instruction has branched !!!)
)
- At the start of the cycle, the CPU sends out value
PC which is the address
of th branch instruction "BRA Label"
- The value PC will also be sent
to the input of the PC1 register:
- At the end of the cycle, the following registers (of interest)
are updated simultaneously: PC register with the value
PC+4,
PC1 register with the value PC and
IR(ID) with the "BRA Label" instruction.
- The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)
- At the start of the cycle, the CPU sends out value
PC+4 which is the address
of th branch instruction "add r2, r1, r2"
- The adder circuit in the ID stage will add
the value PC in the PC1 register
and the offset in instruction register IR(ID) to form
the target address "Label".
- The branch condition code in the ID stage (unconditioncal branch)
will cause the SELECT circuitry in the ID stage
to select PC + offset
for the PC register in the IF stage.
- In the mean time, the IF stage has been sending out
PC+4 and the memory is busy fetching
the "add r2, r1, r2" instruction for the CPU:
- At the end of the cycle, the following registers (of interest)
are updated simultaneously: PC register with the value
Label
(= PC+offset),
IR(EX) with the "BRA Label" instruction and
IR(ID) with the "add r2, r1, r2" instruction:
- The picture above depicts the content of the CPU at end of the first
CPU cycle (and the start of the 2nd cycle)
- The BRANCH instruction has executed - with one instruction delay
- Note: The execution of the "BRA Label" instruction has been completed, and yet the "BRA Label" will continue through the rest of the pipeline stages, but since this instruction will not update any registers, it is not harmful and cause errors later in the pipeline stage.
Demo: /home/cs355000/demo/SPARC/sparc-DELAY-BRANCH.s
(Must run on compute !!!!!)
Compile: cc -o sparc-DELAY-BRANCH sparc-DELAY-BRANCH.s