- The make utility:
- The make application in UNIX
can use the time stamps
of the source file and the
object file to determine
if a some source files need to be
re-compiled
- Furthermore, the make utility
can use the target dependency rules and
a list of associated commands
stored in the file:
makefile or: Makefile (if makefile is not found)to taylor the precise actions that need to be performed.
- The make application in UNIX
can use the time stamps
of the source file and the
object file to determine
if a some source files need to be
re-compiled
- Suppose we have a C program that
consists of one single program file:
File: "hello.c" #include <stdio.h> int main( int argc, char* argv[] ) { printf( "Hello World !\n" ); }
- Dependency of the various files
to produce an executable program:
Source file: hello.c | | gcc -c hello.c | V Object file: hello.o | | gcc -o hello hello.o | V Executable: helloMy Terminology: "dependent" file and "depend on" file
hello depends on hello.o ^ ^ | | "dependent" file "depend on" fileSummary:
hello depends on hello.o Command to update hello when hello.o is changed: gcc -o hello hello.o hello.o depends on hello.c Command to update hello.o when hello.c is changed: gcc -c hello.c hello.c: is changed/updated by the programmer...
- Make file:
- Make file =
a file that contains:
- the dependency relationship between
files, and
- the command(s) used to update the dependent file when it's depend-on file(s) is updated
- the dependency relationship between
files, and
- The name of a
Make file must be equal to:
makefile or: Makefile
- Make file =
a file that contains:
- Example:
file dependency
Source file: hello.c | | gcc -c hello.c | V Object file: hello.o | | gcc -o hello hello.o | V Executable: hello - Corresponding Make
file:
hello: hello.o # Meaning: target hello depends of hello.o <TAB> gcc -o hello hello.o # Command to make the target hello.o: hello.c # Meaning: target hello.o depends of hello.c <TAB> gcc -c hello.c # Command to make the target
- The Make utility:
- Make application = a program that reads in the file dependencies in a Make file and execute the commands when the dependent file has a more recent timestamp than the depend-on file
Example:
Source file: hello.c <==== We update thsi file | | gcc -c hello.c | V Object file: hello.o | | gcc -o hello hello.o | V Executable: helloThe Make utility will then:
- Run gcc -c hello.c to update
hello.o
- Then run gcc -o hello hello.o to update hello
- Example Program:
(Demo above code)
- The hello.c Prog file: click here
- The Makefile: click here
How to run the program:
- Right click on link(s) and
save in a scratch directory
- To compile: make
- Result:
- The first time we run
make, you will see:
UNIX>> make gcc -c hello.c gcc -o hello hello.o
and the make utility creates the target hello
- Now, run make
again, and you will see:
UNIX>> make `hello' is up to date.
The make utility has determined that hello is more recent than the source file hello.c and skip the compilation process !!!
- Next, edit hello.c
(add a space somewhere in the program),
save it and then run
make again:
UNIX>> make gcc -c hello.c gcc -o hello hello.o
The make utility has determined that hello is stale and runs the command(s) to re-compile the source file hello.c !!!
- The first time we run
make, you will see:
- Fact:
- Each file has a
modification timestamp
- Use:
ls -l -rwxr-xr-x 1 cheung staff 6492 Nov 14 19:39 hello* -rw-r--r-- 1 cheung staff 92 Nov 14 19:39 hello.c -rw-r--r-- 1 cheung staff 708 Nov 14 19:39 hello.oto see the modification time
- Each file has a
modification timestamp
- General format of a Makefile:
# Comment lines can appear anywhere Macros section (will be discussed later) Rules section
- Macros section:
- Contains zero or more macro definition(s)
We will discuss macros later in this webpage
- Rule section:
- Contains one or more rule(s)
- Rules:
- A rule tells the make utility when and how to make a target
- Syntax of a rule:
targetName : depend-file1 depend-file2 .... <TAB> UNIX-command-1 <TAB> UNIX-command-2 ... <TAB> UNIX-command-NMeaning:
- The target filename
targetName depends on the
source files
depend-file1,
depend-file2, ...
- When one or more of the
depend files has a
newer time stamp,
the make utility will
execute the
UNIX commands
UNIX-command-1,
UNIX-command-2, ...
UNIX-command-N
- Note:
- You are responsible for make sure that the commands UNIX-command-1, UNIX-command-2, ... UNIX-command-N will correctly create the target targetName
- The target filename
targetName depends on the
source files
depend-file1,
depend-file2, ...
- Example:
hello.o: hello.c # Meaning: target hello.o depends of hello.c <TAB> gcc -c hello.c # Command to keep the target up to date
Meaning:
- The target file hello.o
depends on the (single) source file
hello.c
- If the source file
hello.c has a
newer time stamp
(changed recently !), then the
make utility will execute:
gcc -c hello.c
to keep the target file hello. up to date
- The target file hello.o
depends on the (single) source file
hello.c
- Now consider a C program that consists of
2 program files:
- We have a C program that consists of
2 program files:
- func5a.c
- func5b.c
The header file for func5b.c is:
- func5b.h
- The final executable file
that we want to create is called:
- main
This is the target
- The following figure shows the
dependencies between the
different files:
- We have a C program that consists of
2 program files:
- We can now create the follow Makefile
that represents the
above dependencies:
main: func5a.o func5b.o # main depends on func5a.o and func5b.o gcc -o main func5a.o func5b.o func5a.o: func5a.c # func5a.o depends on func5a.c gcc -c func5a.c func5b.o: func5b.c gcc -c func5b.c func5a.c: func5b.h touch func5a.c func5b.c: func5b.h touch func5b.c
Note:
- The command touch file
updates the
modification time time of the file
file to the
current time
(The newer time stamp will trigger the maintenance command for the file file !!!)
- The command touch file
updates the
modification time time of the file
file to the
current time
- Alternately, we can remove the
touch command by
short-circuiting the
dependencies:
main: func5a.o func5b.o # main depends on func5a.o and func5b.o gcc -o main func5a.o func5b.o func5a.o: func5a.c func5b.h # func5a.o depends on func5a.c gcc -c func5a.c # and (indirectly) also on func5b.h func5b.o: func5b.c func5b.h gcc -c func5b.c
- Example Program:
(Demo above code)
- The func5a.c Prog file: click here
- The func5b.c Prog file: click here
- The func5b.h header file: click here
- The Makefile: click here
How to run the program:
- Right click on link(s) and
save in a scratch directory
- To compile: make
- To run: main
- Result:
- The first time we run
make, you will see:
UNIX>> make gcc -c func5a.c gcc -c func5b.c gcc -o main func5a.o func5b.o
and the make utility creates the target main
- Now, run make
again, and you will see:
UNIX>> make `main' is up to date.
The make utility has determined that main is more recent than the dependency file func5a.o and func5b.o and skips the compilation process !!!
- Next, edit func5a.c
(add a space somewhere in the program),
save it and then run
make again:
UNIX>> make gcc -c func5a.c gcc -o main func5a.o func5b.o
The make utility has determined that func5a.o is stale and runs the command(s) to re-compile the source file func5a.c and link the object files to main !!!
- Now, edit header file
func5b.h
(add a space somewhere in the program),
save it and then run
make again:
UNIX>> make gcc -c func5a.c gcc -c func5b.c gcc -o main func5a.o func5b.o
The make utility re-compiles both func5a.c and func5b.c because of the following dependencies specified in the Makefile:
func5a.o: func5a.c func5b.h gcc -c func5a.c func5b.o: func5b.c func5b.h gcc -c func5a.c
- The first time we run
make, you will see:
- You have
already
seen a multi-targets
makefile !!
- Example: There are
3 targets
(main,
func5a.o and
func5b.o) in the following
makefile:
main: func5a.o func5b.o gcc -o main func5a.o func5b.o func5a.o: func5a.c func5b.h gcc -c func5a.c func5b.o: func5b.c func5b.h gcc -c func5b.c
- Using make for a specific target:
make targetName # Make the target targetNameI.e.: we can make different targets by using an additional argument to the make command !
Example:
make func5a.o make func5b.o make main
- The default target:
- Default target =
the target used by make when
the user has not specified
a specific target
- Default target used by the make utility = the first target specified inside a Makefile
Example:
- Makefile:
main: func5a.o func5b.o gcc -o main func5a.o func5b.o func5a.o: func5a.c func5b.h gcc -c func5a.c func5b.o: func5b.c func5b.h gcc -c func5b.c
- The default target is main.
- Default target =
the target used by make when
the user has not specified
a specific target
- Inference rules
- Inference rule = a generalized rule that can be applied to a group of files with similar file names
- Special notations
used to formulate inference rules:
% = wildcard character - match 0 or more characters $< = first item in the list of dependent filenames $^ = all items in the list of dependent filenames $@ = current target name including the extension $* = current target name not including the extension
- Example: inference rule
%.o: %.c func5b.h gcc -c $<Meaning:
- The character % is
the wildcard character
% matches 0 or more characters in a file name
- Any file
with name "*.o" depends
on a file with same prefix but ends
in
".c" (and also on
the header file
func5b.h)
Example:
%.o: %c func5b.h Will generate all these dependencies: file1.o: file1.c func5b.h file2.o: file2.c func5b.h file3.o: file3.c func5b.h .... anyFilename.o: sameFileName.c func5b.h - The command used to
create the
target "filenameX.o" is:
gcc -c filenameX.c
- The character % is
the wildcard character
- Previously, we used the following
Makefile:
main: func5a.o func5b.o gcc -o main func5a.o func5b.o func5a.o: func5a.c func5b.h gcc -c func5a.c func5b.o: func5b.c func5b.h gcc -c func5b.c
- We can replace the
last 2 rules with
one inference rule:
main: func5a.o func5b.o gcc -o main func5a.o func5b.o %.o: %.c func5b.h gcc -c $<Note: this Makefile is even better
main: func5a.o func5b.o gcc -o $@ $^ %.o: %.c func5b.h gcc -c $<
- Example Program:
(Demo above code)
- The func5a.c Prog file: click here
- The func5b.c Prog file: click here
- The func5b.h header file: click here
- The Makefile: click here
How to run the program:
- Right click on link and
save in a scratch directory
- To compile: make
- To run: main
- Contination character:
- \ =
the continuation character
in a Make file
- Meaning:
- If \ is the last character on a line in a Make file, then the current line will continue onto the next line
- Usage:
- To specify a long list of
dependent files
Example:
main: file1.o file2.o file3.o file4.o file5.o \ <TAB> file6.o file7.o ....
- To specify a lengthy
maintenance command
Example:
main: file1.o <TAB> gcc -o main -D=Define -D=These -D=Options \ <TAB> -I/home/cheung/myInclude/Dir -L/home/cheung/MyLib -lm \ <TAB> file.o
- To specify a long list of
dependent files
- \ =
the continuation character
in a Make file
- Comment
- Any text after the character # will be ignored
- Recal the structure of
a makefile:
# Comment lines can appear anywhere Macros section (will be discussed later) Rules section
- Macros section:
- Contains zero or more macro definition(s)
We will now discuss macros...
(You have seen the rules section)
- Macro:
- Macro = a
pattern that can be expanded
into a (usually) larger number of
patterns
- In other words: Macro = an abbreviated representation of a (usually larger) set of instructions
- Macro = a
pattern that can be expanded
into a (usually) larger number of
patterns
- Syntax of a
macro definition in makefile:
src-pattern = replacement-pattern
Meaning:
- When the pattern
$(src-pattern)is found inside a rule of a makefile, it will be replaced with the pattern:
replacement-pattern
Purpose:
- Macros can enhance the flexibility of the rules inside a makefile
- When the pattern
- Fact:
- There are many
different C compilers.
Examples:
- GNU compiler: gcc
- Solaris compiler: cc
- Microsoft C: Visual C++
- ...
- Each C compiler is invoked with a different command name and different command line options
- There are many
different C compilers.
- Use macros
to adpat a makefile
for different C compiler:
CC=gcc # Compiler command CFLAGS=-c # Compiler options OFLAG=-o # Output flag main: func5a.o func5b.o $(CC) $(OFLAG) main func5a.o func5b.o %.o: %.c func5b.h $(CC) $(CFLAGS) $<
- Example Program:
(Demo above code)
- The func5a.c Prog file: click here
- The func5b.c Prog file: click here
- The func5b.h header file: click here
- The Makefile: click here
How to run the program:
- Right click on link and
save in a scratch directory
- To compile: gcc xx.c
- To run: ./a.out
- Change to different platform:
- When you want to compile
the C program on a different
platform (using a
different C compiler), all you need to do is:
- Update the
macro definitions
inside the makefile
- and.... Make.
- Update the
macro definitions
inside the makefile
- When you want to compile
the C program on a different
platform (using a
different C compiler), all you need to do is: