CS355 Sylabus

Examples of execution of mirco instructions

Sequencing - under direction of the 4 phase clock - will activate different parts of the datapath at different times.
The bits in the micro instructions sets up the swicthes in the datapath and make the data "flow" in different directionrs.
Let us consider the full picture and see:
1. how the datapath is setup by the bits in the micro instruction
2. and how the datapath - under direction of the 4 phase clock - move the data through the datapath under various settings
There are 3 types of data flows through the datapath (I mentioned it before: click here)
- Register-to-register operation (does not involve memory)
- Register-to-memory (write)
- Memory-to-register (read)
We will study the setting and the data flow in each case and analyse the micro-instructions used in each case to setup the datapath.
You must realise that in each case, the datapath is sequenced the same way, namely under the direction of the 4-phase clock. And yet, the datapath will behave (operate) differently due to the setting made by the bits in the micro-instruction.

Register-to-register operation: R5 = R1 + R2

The MIR in the following figure shows the micro-instruction that performs "R5 = R1 + R2" and the figure shows the steps/events that will happen in the datapath when this micro-instruction is executed:

You have to study the bits in the MIR very carefully. Each bit controls some part of the datapath.
Remember also that different parts of the CPU are activated (instructed to update itself) at different times - in the order given by the 4-phase clock. So looking in the above figure, and following the signals of the 4-phase clock, you will see the following happening (I have colored the different parts that are updated with 4 different colors to make things easier to follow):
- Phase 1: The "next" micro instruction is loaded into the MIR and the MIR sends out control signals immediately.
  The control signals that is important in phase 1 are the A and B fields, which select the registers 0001 (R1) and 0010 (R2)
  BTW: the reason why these signals are important in phase 1 is because the A- and B-latches are updated in the next phase and the input input the A- and B-latches are selected by the A and B fields.
- Phase 2: A- and B-latches are updated and captures the values of R1 and R2 and keep these values for the remainder of the CPU cycle.
- Phase 3: phase 3 has 2 different uses in different micro-instructions. The first use is to allow the ALU and Shifter time to do the computation - which is happening in this example.
  The second use of phase 3 is to update the MAR, this does not happen in this micro-instruction. We will see one such instruction below.
- Phase 4: in phase 4, the result is written to the destination. The destination can be a register or the MBR (in the case of a memory write instruction). In this example, register R5 (0101 indicates register 5) will be updated because ENC bit = 1. On the other hand, the MBR is not updated because the MBR bit in the MIR is equal to 0.
- In summary: R1 and R2 are first copied into A- and B-latches, the ALU is instructed to add, the shifter does no shift, the result on the C-bus is thus R1 + R2, and this result is written into register R5.
NOTE: you can use cs355-demo-dp2 to see this instruction in life action. Select instruction 3.

Write operation: MOV R1, (R2)

The MIR in the following figure shows the micro-instruction that performs "MOV R1, (R2)" - move data in R1 to memory location whose address is given in R2. The figure shows the steps/events/things that will happen in the datapath when this micro-instruction is executed:

Again, study the bits in the MIR very carefully first. I will now guide you through the execution.... The datapath is going to do the same things again as the previous example. However, because values of the different controlling bits are different, different things will happen !
- Phase 1: The "next" micro instruction is loaded into the MIR and the MIR sends out control signals immediately.
  The control signals that is important in phase 1 are the A and B fields, which select the registers 0001 (R1) and 0010 (R2)
- Phase 2: A- and B-latches are updated and captures the values of R1 and R2 and keep these values for the remainder of the CPU cycle.
- Phase 3: during phase 3, the ALU and Shifter gets time to do the computation - in this example, the ALU will output the first input (= R1) and the Shifter will not shift, so that the result R1 is produced on the C-bus
  Simultaneously, the MAR is updated with the value of the B-latch (= R2) because the MAR bit in the micro-instruction is 1 and allow the phase 3 clock to trigger update to the MAR.
- Phase 4: in phase 4, the result on the C-bus (= R1) is written to the destination. The destination in this example is the MBR and not any register - you can tell this from the fact that the MBR bit of the micro-instruction is 1 (update MBR) and the ENC bit is 0 (do not update any register).
- In summary: R1 is copied into MBR and R2 is copied into MAR.
Notes:
- The data has not yet been written to the memory !!!
  Following this micro-instruction, the CPU will pause until the data in the MBR has been transfered to memory. The transference of data proceeds under a very rigid sequence of operation called "bus protocol". Bus protocols will be studied after we completed the discussion on the CPU architecture
- You can pause the CPU in different ways. The simplest way is stop the 4-phase clock.
  But sometimes it is necessary to run the CPU to "refresh" the data stored in various registers. In that case, a "dummy" micro-instruction can be used to run the CPU that "does not do any harm". You can only do harm when you update values in registers.... So by blocking out all the update bits MAR, MBR and ENC in the micro-instruction, the datapath will do the transfer and compute normally, but the result will not be used to update any register.
  The following is an example of a "dummy" micro-instruction that make the datapath go through its normal operational cycle but does not update any registers:

Read operation: MOV (R2), R5

The MIR in the following figures shows the micro-instruction that performs "MOV (R2), R5" - move data from memory location whose address is given in R2 into register R5.
The read operation is somewhat different from the write operation because the CPU needs to wait for the memory to return the data read in MBR before it can proceed to update the destination register (which is R5 in this example)....
The CPU must execute at least two micro-instructions to read data from memory.
Also, depending on how fast the memory can return the data requested, the CPU may or may not need to wait even longer...
Let us consider what needs to be done under the ideal circumstance: when the memory is infinitely fast, i.e., as soon as the memory receives the read request with the proper address, the memory can return the data immediately.
1. The following is the first instruction that is executed by the CPU in a memory read operation:
  
  I will now guide you through the execution.... The datapath is going to do the same things again as the previous example. However, because values of the different controlling bits are different, different things will happen !
  - Remember that: to perform a memory read operation, the CPU needs to send out the address on the address bus and get the memory data into MBR...
  - Phase 1: The "next" micro instruction is loaded into the MIR and the MIR sends out control signals immediately.
    The control signals that is important in phase 1 is the B field, which select the registers 0010 (R2) for the B-latch (because this is how the address will be loaded into the MAR in phase 3).
    Notice that the destination register R5 is not written by this micro-instruction ! The data must come into MBR first before it gets transfered into R5 !
  - Phase 2: B-latch (and A-latch - but A-latch value is not used) will are updated and capture the value of R2 and keep this values for the remainder of the CPU cycle.
  - Phase 3: during phase 3, the ALU and Shifter gets time to do useless computation (yes, it is unavoidable to "waste" things in machines).
    Simultaneously, (and that is what is really important in the read opeartion) the MAR is updated with the value of the B-latch (= R2) because the MAR bit in the micro-instruction is 1 and allow the phase 3 clock to trigger update to the MAR.
  - Phase 4: we have assume that the memory is infinitely fast, so the data from memory will be ready on the databus as soon as the address in MAR is ready - which happens in pahse 3...
    So the data will be ready on the databus during phase 4 and we can update the MBR with the data on data bus.
    The destination in this micro-instruction is the MBR, you can tell this from the fact that the MBR bit of the micro-instruction is 1 (update MBR).
  - In summary: R2 is copied into MAR and immediately the memory retrieves the value from the address given by R2. This value is copied into the MBR.
  Note:
  - The data has not yet been written to register R5 !!!
2. After getting the data from memory into the MBR, the CPU must execute the following micro-instruction to transfer the data from MBR to its final destination register (= R5):

Let use now consider the case in a realistic system when the memory take some time to return the data requested. The main difference is that the CPU cannot perform the MBR update right away and must wait. But the CPU must maintain the READ system and the address (in MAR) constant (so that the memory will not be confused about the CPU's intension).

The first instruction is changed a bit, in that we cannot update MBR during phase 4. The following is the first micro-instruction in a read operating using a "realistic" memory:
The CPU can wait by executing a "do no harm" instruction while maintaining the READ signal active:

Notice that the MAR, MBR amd ENC bits in the micro-instructions are all ZERO ("do no harm"), and the READ bit is ONE (signal reading)
Depending on how fast the memory is, one or more of this "do no harm while reading" micro-instructions can be inserted.
Note that there is no danger in executing too many of these "do no harm while reading" micro-instructions, the only effect is that you slow dowm the CPU (which is not a good thing to do...)
When the data is ready on the databus, the CPU will execute the following instruction to "clock in" (jargon for write) the data into the MBR:
And finally, the data in the MBR is transfered to its final destination (= R5) by using the same micro-instruction that you saw in the first case above ( click here):
Obvious conclusions from these examples is:
- Micro-instructions can make the datapath do different things.
- The amount of work that can be performed under the direction of one micro-instruction is very little.
- A sequence of micro-instructions can be used to perform a more complex task.
- A sequence of micro-instructions is called a micro-program