First, what is the state of the computer:
The first step that the CPU must perform is to fetch the data at address given by the PC register from memory and store it in the IR register.
| Register | Name | Usage |
|---|---|---|
| R0 | Program Counter (PC) | Holds address of next instruction |
| R1 | Accumulator (AC) | Main working/scratch register |
| R2 | Stack pointer (SP) | Points to top of stack |
| R3 | Instruction Register (IR) | Holds currect instruction |
| R4 | Temp Instruction Register (TIR) | Use to decode instruction |
| R5 | 0 (ZERO) | Hardwired Constant (like g0 in SPARC) |
| R6 | +1 (ONE) | Hardwired Constant (like g0 in SPARC) |
| R7 | -1 (MINUS ONE) | Hardwired Constant (like g0 in SPARC) |
| .. | .... | ... |
ADDR Micro Assembler Instruction Comment
===========================================================================
0: mar := pc; rd; {main loop}
1: pc := pc + 1; rd; mbr; {increment pc, MBR}
2: ir := mbr; if n then goto 31; {save, decode mbr}
3: tir := lshift(ir + ir); if n then goto 22;
4: tir := lshift(tir); if n then goto 13; {000x or 001x?}
5: alu := tir; if n then goto 9; {0000 or 0001?}
....
After running the 4-phase clock from phase 1 to phase 4, the datapath would have performed the following:
After running the 4-phase clock from phase 1 to phase 4, the datapath would have performed the following:
After running the 4-phase clock from phase 1 to phase 4, the datapath would have performed the following:
Do the following: