Design of the Pipelined CPU in Logic-SIM

Overview
- In this project you will make 2 pipelined CPUs:
  - The basic pipelined CPU
  - The advanced pipelined CPU
- I will design the CPUs modules in such a way that you can reuse the basic piplelined CPU in the advanced pipelined CPU.
- All you need to do is to add extra multiplexors (with pretty complicated control logic) and other logic circuits between the stages to get the advanced pipelined CPU.
- The Basic Pipelined CPU:

Instruction Format

constant flag Dest | Scr1 Src2 |<--------->| V |<--------->|<--------->| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | A | B | C | D | x | x | x | c | c | f | x | x | x | x | x | x | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |<-------------> |<----->| opcode ^ | cc = ALU opcode 00 = add 01 = subtract 10 = and 11 = not or branch condition 00 = no branch 01 = branch if N = 1 10 = branch if Z = 1 11 = always branch ABCD encodes the operation/instruction as follows: A = 1 ---> LD instruction B = 1 ---> ST instruction C = 1 ---> Branch instruction (cc encode the branch condition) D = 1 ---> SETHI instruction ABC = 0000 ---> ALU instruction (cc encodes the operation) Other combinations are not used (so decoding instruction is very easy)

Obtaining various constants in the instruction

There are 3 kinds of instructions that uses constants embedded inside the instruction:
- ALU instruction
- Sethi instruction
- Branch instruction
Each type of instructions encode their constant differently and we must extract it differently, depending on the instruction type (you guess it, use MUXes...)

The constant used by ALU instructions is contained by the Src2 field:

constant flag Dest | Scr1 Src2 |<--------->| V |<--------->|<--------->| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | | | | | | | | | 1 | | | | x | x | x | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Constant

The SETHI constant is encoded as follows:

Dest |<--------->| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | | | 1 | | | | x | x | x | x | x | x | x | x | x | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Constant

The SETHI instruction shifts the constant over by 3 bits and store the result in the Dest register.

So you should output this value when it is a SETHI instruction:

Forming the SETHI constant: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | | | 1 | | | | a | b | c | d | e | f | g | h | i | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Constant Constant used in operation: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | a | a | a | a | a | b | c | d | e | f | g | h | i | 0 | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Don't use shifters to accomplish this. This can be done easily by "creative connection". Connect the input "shifted over" to a different multiplexer input - just like in a multiply circuit.

The Branch instruction also uses a constant offset and it is encoded as follows:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | | 1 | | x | x | x | x | x | x | x | x | x | x | x | x | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Constant offset

You must sign-extend the constant offset also.

How to extract the differet constants - here's a circuit that illustrates how to extract the various constant depending of the instruction (use Muxes ofcourse...):
You need this "constant extraction circuit" inside the ID stage

How to implement the Basic Pipelined CPU:

The different components (macros) and their connections are given in this figure:
The meaning of the "red dots" in the above figure:
- The "red dots" represent the common way to handle stalling in the pipeline.
- When a stage stalls, it does the following:
  1. Do not generate a clock signal (that write the IR of that stage)
  2. Send a NOP instruction as output
Example 1:
If Stall_IF = 1 then:
1. Do not generate a clock signal that write the IR of the IF stage (since IF does not have an IR register, this step is void)
2. Send a NOP instruction as output to the IR_ID register
Example 2:
If Stall_ID = 1 then:
1. Do not generate a clock signal that write the IR of the ID stage (so the instruction in IR_ID does not change)
2. Send a NOP instruction as output to the IR_EX register

NOTE:

This is extremely important...

By default, all Dff (registers) are written at the END of the clock:



       		+--------+
		|	 |
		|	 |
		|	 |
       +--------+	 +             

			 ^
			 |
			 |
			 |
		   Update Dff (registers)

There are some registers that must be updated in the MIDDLE of the clock:


       		+--------+
		|	 |
		|	 |
		|	 |
       +--------+	 +             

	        ^
	        |
	        |
	        |
	  Update Dff (registers)

I will indicate that explicitly in the design notes.

The "Mux" components are ordinary multiplexors.
Below, I will describe each component:
- IF
- ID
- EX
- MEM
- WR
- Decision circuit D (magenta colored component in diagram)
- Stall logic circuit Stall_IF
- Stall logic circuit Stall_ID
- Stall logic circuit Stall_EX
- Stall logic circuit Stall_MEM

The IF Stage

Schematics:

Macro Definition:

Define IF clk stall branch MemDataIn[15..0] branchAddr[15..0] | MemRq Read PC[15..0] IF_Out[15..0]; ..... Endef;

Memory need:
- 16 bit Dff memory to Prog Counter PC
Constant need:
- 16 bit constant 000...000 that represents NOP instruction
Input signals:
- clk: clock... (you know what to do with it, I omitted the connection from the clock to the Dff's)
- stall: 1 = stall IF stage, 0 = don't stall
- branch: 1 = branch, 0 don't branch
- MemDataIn[15..0]: memory data, which is the instruction from memory
- branchAddr[15..0]: branch destination address
Output signals:
- MemRq = memory request signal for the memory module (must pass through tri-state-buffers)
- Read = read indication signal for the memory module (must pass through tri-state-buffers)
- PC[15..0] = Prog Counter PC (must pass through tri-state-buffers)
  The tri-state-buffers are on when: stall = 0
- IF_Out[15..0] = fetched instruction
Operation:
- if Stall = 1
  - Output NOP instruction
  - do not change PC
  - disable all tri-state-buffers
- if Stall = 0
  - output fetched instruction
  - change PC (use branch input signal to select the proper value for PC: PC+1 or branchAddr[15..0])

The ID Stage

Schematics:

Macro Definition:

Define ID clk IR_ID[15..0] PC[15..0] src1[15..0] src2[15..0] src3[15..0] | src1_sel[0..3] src2_sel[0..3] src3_sel[0..3] PC1[15..0] A[15..0] B[15..0] IR_Const[15..0] D[15..0]; ..... Endef;

Notice there is no stall signal as input to the ID stage - the ID stage will always fecth the operands.
The stalling will only affect the IR_ID register and it is handled by the "red dot" circuitry !
Memory need:
- PC1[15..0]: 16 bit Dff memory to forward PC for Branch instruction
- A[15..0]: 16 bit Dff memory to Src 1 operand
- B[15..0]: 16 bit Dff memory to Src 2 operand
- IR1[15..0]: 16 bit Dff memory to constant operand
- D[15..0]: 16 bit Dff memory to operand for store instruction
Constant need:
- Mask (000..11111) to extract the constant from the instruction
Input signals:
- clk: clock... (you know what to do with it, I omitted the connection from the clock to the Dff's)
- IR_ID[15..0]: instruction from IR_ID register
- PC[15..0]: PC value from IF stage (needed for branch instruction)
- src1[15..0]: reg. src operand 1 selected by src1_sel[0..3]
- src2[15..0]: reg. src operand 2 selected by src2_sel[0..3]
- src3[15..0]: reg. src operand 3 selected by src3_sel[0..3]
Output signals:
- src1_sel[0..3]: used to select src reg. 1 from register bank
- src2_sel[0..3]: used to select src reg. 2 from register bank
- src3_sel[0..3]: used to select src reg. 3 from register bank
- PC1[15..0]: PC value for Branch instruction
- A[15..0]: Src 1 operand
- B[15..0]: Src 2 operand
- IR_Const[15..0]: constant operand in the instruction
- D[15..0]: register operand for store instruction
Operation:
- Write IR_ID[15..0] to PC1[15..0] in the MIDDEL of the clock cycle
- Write AND(Mask, PC[15..0]) to IR1[15..0] in the MIDDEL of the clock cycle
- Write src1[15..0] to A[15..0] in the MIDDEL of the clock cycle
- Write src2[15..0] to B[15..0] in the MIDDEL of the clock cycle
- Write src3[15..0] to D[15..0] in the MIDDEL of the clock cycle
NOTE:
- The "Extract constant" circuit is given above: click here

The EX Stage

Schematics:

Macro Definition:

Define EX clk IR_ID[15..0] src1[15..0] src2[15..0] src3[15..0] | N Z ALUout[15..0] DMAR[15..0] SMDR[15..0]; ..... Endef;

Memory need:
- ALUout[15..0]: 16 bit Dff memory to store result of ALU
- DMAR[15..0]: 16 bit Dff memory to store result of ALU
- SMDR[15..0]: 16 bit Dff memory to store src3[15..0]
Constant need:
- None
ALU operations allowed:
- 00 = add
- 01 = and
- 10 = or
- 11 = not
Input signals:
- clk: clock... (you know what to do with it, I omitted the connection from the clock to the Dff's)
- IR_EX[15..0]: instruction from IR_EX register
- src1[15..0]: src operand 1
- src2[15..0]: src operand 2
- src3[15..0]: src operand 3
Output signals:
- N = negative flag
- Z = zero flag
- ALUout[15..0]: from the ALUout[15..0] register
- DMAR[15..0]: from the DMAR[15..0] register
- SMDR[15..0]: from the SMDR[15..0] register
Operation:
- It's just like the old ALU you made in CS355 - except there is now an OR operation... Should be easy to change....

The MEM Stage

Schematics:

Macro Definition:

Define MEM clk IR_MEM[15..0] src1[15..0] src2[15..0] src3[15..0] | bcc1 bcc0 MemRq Read ALUout[15..0] DMAR[15..0] SMDR[15..0]; ..... Endef;

Memory need:
- ALUout1[15..0]: 16 bit Dff memory to store (forward) data from src1[15..0]
- LMDR[15..0]: 16 bit Dff memory to store data from memory
Constant need:
- None
Input signals:
- clk: clock... (you know what to do with it, I omitted the connection from the clock to the Dff's)
- IR_MEM[15..0]: instruction from IR_MEM register
- src1[15..0]: src operand 1 (which is ALUout from EX stage)
- src2[15..0]: src operand 2 (which is DMAR from EX stage)
- src3[15..0]: src operand 3 (which is SMDR from EX stage)
- MemDataIn[15..0]: operand from memory
Output signals:
- (bcc1, bcc0) = branch condition bits
- MemRq = memory request signal for the memory module (must pass through tri-state-buffers)
- Read = read indication signal for the memory module (must pass through tri-state-buffers)
- ALUout1[15..0]: from the ALUout1[15..0] register
- LMDR[15..0]: from the SMDR[15..0] register
- MemAddrOut[15..0]: memory address - tie src3[15..0] through tri-state-buffers to MemAddrOut[15..0]
  (must pass through tri-state-buffers)
  The tri-state-buffers for MemAddrOut[15..0] are on when: instruction in MEM stage is LD or ST
- MemDataOut[15..0]: operand from/to memory
  - Tie Dff inputs into directly to the memory outputs
  - Tie Dff outputs through tri-state-buffers to the memory inputs
    (must pass through tri-state-buffers)
  The tri-state-buffers for MemDataOut[15..0] are on when: instruction in MEM stage is ST
Operation:
- MemRq = (LD == 1) OR (ST == 1)
- Read = ((LD == 1) OR (ST == 1)) AND (LD == 1)
- LD:
  1. Activate MemAddrOut[15..0] tri-state-buffers
  2. De-activate MemDataOut[15..0] tri-state-buffers
  3. Activate MemRq signal's tri-state-buffers
  4. Activate Read signal's tri-state-buffers
- ST:
  1. Activate MemAddrOut[15..0] tri-state-buffers
  2. Activate MemDataOut[15..0] tri-state-buffers
  3. Activate MemRq signal's tri-state-buffers
  4. Activate Read signal's tri-state-buffers
- Not LD or ST:
  1. De-activate MemAddrOut[15..0] tri-state-buffers
  2. De-activate MemDataOut[15..0] tri-state-buffers
  3. De-activate MemRq signal's tri-state-buffers
  4. De-activate Read signal's tri-state-buffers
- It's OK to update LMDR[15..0] all the time. Because if you write garbage in LMDR[15..0], (happens on a non-LD instruction), the WR-stage will not use LMDR[15..0] to update the registers anyway.

The WR Stage

Schematics:

Macro Definition:

Define WR clk IR_WR[15..0] src1[15..0] src2[15..0] | C_Enable RegSel[0..2] CBus[15..0]; ..... Endef;

Memory need:
- None.
Constant need:
- None
Input signals:
- clk: clock... (you know what to do with it, I omitted the connection from the clock to the Dff's)
- IR_WR[15..0]: instruction from IR_WR register
- src1[15..0]: src operand 1 (which is ALUout from MEM stage)
- src2[15..0]: src operand 2 (which is SMDR from MEM stage)
Output signals:
- C_Enable = CBus write signal (1 = write a register, 0 don't write any register)
- RegSel[2..0] = Register select
- RegData[15..0]: data for the register
Operation:
- CBus = 0: Send signals to do nothing to register
- CBus = 1: Send signals to update selected register

The PSR

Macro Definition:

Define PSR clk N_in Z_in | N Z; ... 2 Dff's Endef;

Memory need:
- 2 Dffs
Input signals:
- clk: clock...
- N_in: N flag input
- Z_in: Z flag input
Output signals:
- N: N flag
- Z: Z flag
Operation:
- Always update N and Z flags.
- Make sure the N and Z flags are updated in the middle of the clock

The Registers

Macro Definition:

Define Registers clk CBus RegSel[2..0] DataIn[15..0] | Reg7[15..0] Reg6[15..0] Reg5[15..0] Reg4[15..0] Reg3[15..0] Reg2[15..0] Reg1[15..0] Reg0[15..0]; Endef;

Memory need:
- 8 x 16 Dffs
Input signals:
- clk: clock...
- CBus: 0 = don't write, 1 = write a register
- RegSel[2..0]: select the register for writing
- DataIn[15..0]: Data input for writing register
Output signals:
- Reg0 to Reg7
- Reg0[15..0] is the constant 0
Operation:
- Very straightforward... update the selected register when CBus = 1.
- Make sure the register is updated in the middle of the clock

The Branch Decision Circuit D

Macro Definition:

Define BranchDecision ccN ccZ N Z | branch ; .... Endef;

Input signals:
- ccN = condition code N (from instruction opcode)
- ccZ = condition code Z (from instruction opcode)
- N = N flag (from PSR)
- Z = Z flag (from PSR)
Output signals:
- branch = 0, no branch
- branch = 1, branch

Operation:

ccN ccZ N Z | branch ---------------------------+---------- 0 0 0 0 | 0 0 0 0 1 | 0 0 0 1 0 | 0 0 0 1 1 | 0 ---------------------------+---------- 0 1 0 0 | 0 0 1 0 1 | 1 0 1 1 0 | 0 0 1 1 1 | 1 ---------------------------+---------- 1 0 0 0 | 0 1 0 0 1 | 0 1 0 1 0 | 1 1 0 1 1 | 1 ---------------------------+---------- 1 1 0 0 | 1 1 1 0 1 | 1 1 1 1 0 | 1 1 1 1 1 | 1

The Stall_IF circuit

Macro Definition:

Define Stall_IF ID_stall IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] | stall ; .... Endef;

Input signals:
- ID_stall = stall output signal from the ID stage
- IR_ID[15..0] = instruction in ID stage
- IR_EX[15..0] = instruction in EX stage
- IR_MEM[15..0] = instruction in MEM stage
Output signals:
- stall = 0, no stall
- stall = 1, stall
Operation:
- set stall = 1 when:
  1. ID_Stall = 1 or
  2. IR_MEM[15] = 1 (load) or
  3. IR_MEM[14] = 1 (store)

The Stall_ID circuit

Macro Definition:

Define Stall_ID EX_stall IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] | stall ; .... Endef;

Input signals:
- EX_stall = stall output signal from the EX stage
- IR_ID[15..0] = instruction in ID stage
- IR_EX[15..0] = instruction in EX stage
- IR_MEM[15..0] = instruction in MEM stage
Output signals:
- stall = 0, no stall
- stall = 1, stall
Operation:
- set stall = 1 when:
  1. EX_Stall = 1

The Stall_EX circuit

Macro Definition:

Define Stall_EX MEM_stall IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] | stall ; .... Endef;

Input signals:
- MEM_stall = stall output signal from the MEM stage
- IR_ID[15..0] = instruction in ID stage
- IR_EX[15..0] = instruction in EX stage
- IR_MEM[15..0] = instruction in MEM stage
Output signals:
- stall = 0, no stall
- stall = 1, stall
set stall = 1 when:
1. MEM_Stall = 1

The Stall_MEM circuit

Macro Definition:

Define Stall_MEM IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] | stall ; .... Endef;

Input signals:
- IR_ID[15..0] = instruction in ID stage
- IR_EX[15..0] = instruction in EX stage
- IR_MEM[15..0] = instruction in MEM stage
Output signals:
- stall = 0, no stall
- stall = 1, stall
Operation:
- always output stall = 0
  (I made it like this, so future extensions that require ID stage to be stalled, can be easily added)

The BasicPipe circuit

Schematics:

Macro Definition:

Define BasicPipe clk reset DatabusIn[15..0] | PC[15..0] N Z branch MemRq Read AddrBusOut[15..0] DataBusOut[15..0] Stall_IF Stall_ID Stall_EX Stall_MEM IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] IR_WR[15..0] Reg0[15..0] Reg1[15..0] Reg2[15..0] Reg3[15..0] Reg4[15..0] Reg5[15..0] Reg6[15..0] Reg7[15..0] IF_PC[15..0] IF_IF_Out[15..0] ID_PC1[15..0] ID_A[15..0] ID_B[15..0] ID_Const[15..0] ID_D[15..0] EX_Op1[15..0] EX_Op2[15..0] EX_ALUout[15..0] EX_DMAR[15..0] EX_SMDR[15..0] MEM_ALUout[15..0] MEM_LMDR[15..0] WR_C_Enable WR_RegSel[2..0] WR_CBus[15..0] Endef;

Input signals:
- clk = clock
- reset = reset signal (set PC to 0)
- DatabusIn[15..0] = data from Databus
Output signals:
- PC[15..0] = Value of PC (in IF stage)
- N = N flag (from PSR)
- Z = Z flag (from PSR)
- branch = branch decision (from Branch Decision Circuit D)
- MemRq = Memory Request (OR result of MemRq from IF stage and MemRq from MEM stage)
- READ = Read (OR result of Read from IF stage and Read from MEM stage)
- AddrBusOut[15..0] = addres value (each bit AddrBusOut[i] is the OR result of AddrBusOut[i] from IF stage and AddrBusOut[i] from MEM stage)
- DataBusOut[15..0] = addres value (each bit DataBusOut[i] is the OR result of DataBusOut[i] from IF stage and DataBusOut[i] from MEM stage)
- Stall_IF, Stall_ID, Stall_EX, Stall_MEM = Stall indicators (outputs of the Stall Circuits)
- IR_ID[15..0], IR_EX[15..0], IR_MEM[15..0], IR_WR[15..0] = values in the instruction registers in the ID, EX, MEM and WR stages. (These are the outputs of 16 bit Dffs of the 4 Instruction registers)
- Reg0[15..0], Reg1[15..0], ..., Reg8[15..0] = registers
- IF_PC[15..0] = Output of the IF stage: the PC output
- IF_IF_Out[15..0] = Output of the IF stage: the IF_IF_Out output
- ID_PC1[15..0] = Output of the ID stage: the PC1 output
- ID_A[15..0] = Output of the ID stage: the A output
- ID_B[15..0] = Output of the ID stage: the B output
- ID_Const[15..0] = Output of the ID stage: the IR_Const output
- ID_D[15..0] = Output of the ID stage: the D output
- EX_Op1[15..0] = Output of the pre-EX stage multiplexor: Operand 1
- EX_Op2[15..0] = Output of the pre-EX stage multiplexor: Operand 2
- EX_ALUout[15..0] = Output of the EX stage: the ALUout output
- EX_DMAR[15..0] = Output of the EX stage: the DMAR output
- EX_SMDR[15..0] = Output of the EX stage: the SMDR output
- MEM_ALUout[15..0] = Output of the ME stage: the ALUout output
- MEM_LMDR[15..0] = Output of the ME stage: the LMDR output
- WR_C_Enable = C_Enabled signal (write register)
- WR_RegSel[2..0] = Register select (one of 8)
- WR_CBus[15..0]
Operation:
- If wired correctly, I hope the CPU will work (if I did not make any design error :-))