Define AdvPipe clk reset DatabusIn[15..0] |
	  PC[15..0] N Z branch
	  MemRq Read AddrBusOut[15..0] DataBusOut[15..0]
	  Stall_IF  Stall_ID  Stall_EX Stall_MEM
	  IR_IF[15..0] IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] IR_WR[15..0]
	  Reg0[15..0] Reg1[15..0] Reg2[15..0] Reg3[15..0]
	  Reg4[15..0] Reg5[15..0] Reg6[15..0] Reg7[15..0]
	  IF_PC[15..0] IF_IF_Out[15..0] 
	  ID_PC1[15..0] ID_A[15..0] ID_B[15..0] ID_Const[15..0] ID_D[15..0]
	  EX_Op1[15..0] EX_Op2[15..0]
	  EX_ALUout[15..0] EX_DMAR[15..0] EX_SMDR[15..0]
	  MEM_ALUout[15..0] MEM_DMAR[15..0] MEM_SMDR[15..0]
	  WR_C_Enable WR_RegSel[2..0] WR_CBus[15..0]
	  Tag1[2..0] Value1[15..0] Tag2[2..0] Value2[15..0];


Or aa ONE Reg0[0]; Or aa ONE Reg0[1]; Or aa ONE Reg0[2]; Or aa ONE Reg0[3];
Or aa ONE Reg0[4]; Or aa ONE Reg0[5]; Or aa ONE Reg0[6]; Or aa ONE Reg0[7];
Or aa ONE Reg0[8]; Or aa ONE Reg0[9]; Or aa ONE Reg0[10]; Or aa ONE Reg0[11];
Or aa ONE Reg0[12]; Or aa ONE Reg0[13]; Or aa ONE Reg0[14]; Or aa ONE Reg0[15];

Endef;