/* --------------- Test circuit for basic pipelined CPU --------------- */


#include "basic.h"
#include "mem.h"

#include "IF.h"
#include "ID.h"
#include "EX.h"
#include "MEM.h"
#include "WR.h"
#include "stall.h"

#include "PSR.h"
#include "regs.h"
#include "BraDecision.h"

#include "BasicPipe.h"


BasicPipe ph clk reset DatabusIn[15..0] |
	  PC[15..0] N Z branch
	  MemRq Read AddrBusOut[15..0] DataBusOut[15..0]
	  Stall_IF  Stall_ID  Stall_EX Stall_MEM
	  IR_IF[15..0] IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] IR_WR[15..0]
	  Reg0[15..0] Reg1[15..0] Reg2[15..0] Reg3[15..0]
	  Reg4[15..0] Reg5[15..0] Reg6[15..0] Reg7[15..0]
	  IF_PC[15..0] IF_IF_Out[15..0] 
	  ID_PC1[15..0] ID_A[15..0] ID_B[15..0] ID_Const[15..0] ID_D[15..0]
	  EX_Op1[15..0] EX_Op2[15..0]
	  EX_ALUout[15..0] EX_DMAR[15..0] EX_SMDR[15..0]
	  MEM_ALUout[15..0] MEM_DMAR[15..0] MEM_LMDR[15..0]
	  WR_C_Enable WR_RegSel[2..0] WR_CBus[15..0];

Memory ph MemRq Read AddrBusOut[15..0] DataBusOut[15..0] | DatabusIn[15..0];

/* Probes */

/* Row 1: PC, PSR, registers */

Byte-probe-h "PC" ab-ac PC[15..8]; Byte-probe-h ad-ae PC[7..0];

Probe  "Mem"  bb MemRq;
Probe  "RD"   bc Read;

Byte-probe-h "Mem" cb-cc DatabusIn[15..8]; Byte-probe-h cd-ce DatabusIn[7..0];

Probe  "Bra" ag branch;

Byte-probe-h "Bra" ah-ai EX_ALUout[15..8]; Byte-probe-h aj-ak EX_ALUout[7..0];

Probe  "N" dl N;
Probe  "Z" el Z;

Byte-probe-h "R0" an-ao Reg0[15..8]; Byte-probe-h ap-aq Reg0[7..0];
Byte-probe-h "R1" bn-bo Reg1[15..8]; Byte-probe-h bp-bq Reg1[7..0];
Byte-probe-h "R2" cn-co Reg2[15..8]; Byte-probe-h cp-cq Reg2[7..0];
Byte-probe-h "R3" dn-do Reg3[15..8]; Byte-probe-h dp-dq Reg3[7..0];

Byte-probe-h "R4" as-at Reg4[15..8]; Byte-probe-h au-av Reg4[7..0];
Byte-probe-h "R5" bs-bt Reg5[15..8]; Byte-probe-h bu-bv Reg5[7..0];
Byte-probe-h "R6" cs-ct Reg6[15..8]; Byte-probe-h cu-cv Reg6[7..0];
Byte-probe-h "R7" ds-dt Reg7[15..8]; Byte-probe-h du-dv Reg7[7..0];


/* Row 2: Outputs of the stages */

/* IF */
Byte-probe-h "PC   " oc-od PC[15..8]; 
           Byte-probe-h oe-of PC[7..0];
Byte-probe-h "Instr" pc-pd DataBusOut[15..8]; 
           Byte-probe-h pe-pf DataBusOut[7..0];

/* ID */
Byte-probe-h "PC1     " ie-if ID_PC1[15..8]; 
           Byte-probe-h ig-ih ID_PC1[7..0];
Byte-probe-h "A       " je-jf ID_A[15..8]; 
           Byte-probe-h jg-jh ID_A[7..0];
Byte-probe-h "B       " ke-kf ID_B[15..8]; 
           Byte-probe-h kg-kh ID_B[7..0];
Byte-probe-h "Const   " le-lf ID_Const[15..8]; 
           Byte-probe-h lg-lh ID_Const[7..0];
Byte-probe-h "D       " me-mf ID_D[15..8]; 
           Byte-probe-h mg-mh ID_D[7..0];


/* Mux outputs */
Byte-probe "Op1" fi-hi EX_Op1[0..7];
Byte-probe       ii-ki EX_Op1[8..15];

Byte-probe "Op2" mi-oi EX_Op2[0..7];
Byte-probe       pi-ri EX_Op2[8..15];

/* ALU outputs */

Byte-probe-h "ALU     " jk-jl EX_ALUout[15..8];
           Byte-probe-h jm-jn EX_ALUout[7..0];

Byte-probe-h "DMAR    " mk-ml EX_DMAR[15..8];
           Byte-probe-h mm-mn EX_DMAR[7..0];

Byte-probe-h "SMDR    " qk-ql EX_SMDR[15..8];
           Byte-probe-h qm-qn EX_SMDR[7..0];


/* MEM outputs */

Byte-probe-h "ALU     " ko-kp MEM_ALUout[15..8];
           Byte-probe-h kq-kr MEM_ALUout[7..0];

Byte-probe-h "Addr    " no-np MEM_DMAR[15..8];
           Byte-probe-h nq-nr MEM_DMAR[7..0];

Byte-probe-h "LMDR    " po-pp MEM_LMDR[15..8];
           Byte-probe-h pq-pr MEM_LMDR[7..0];


/* WR outputs */

Byte-probe-h "Data    " js-jt WR_CBus[15..8];
           Byte-probe-h ju-jv WR_CBus[7..0];

Probe  "C-En"  hu  WR_C_Enable;

Probe  "C2"  gt  WR_RegSel[2];
Probe  "C1"  gu  WR_RegSel[1];
Probe  "C0"  gv  WR_RegSel[0];




/* Row 3: IR of the stages */

Byte-probe-h "ID     "  se-sf ID_PC1[15..8];
           Byte-probe-h sg-sh ID_PC1[7..0];

Byte-probe-h "EX     "  tk-tl ID_PC1[15..8];
           Byte-probe-h tm-tn ID_PC1[7..0];

Byte-probe-h "MEM    "  so-sp ID_PC1[15..8];
           Byte-probe-h sq-sr ID_PC1[7..0];

Byte-probe-h "WR     "  ts-tt ID_PC1[15..8];
           Byte-probe-h tu-tv ID_PC1[7..0];



Probe  "*IF"   ud Stall_IF;
Probe  "*ID"   ug Stall_ID;
Probe  "*EX"   um Stall_EX;
Probe  "*MEM"  uq Stall_MEM;


Switch "0:Rst"    ru reset ZERO;
Switch "1:Clk"    rv clock ZERO;