- We will first present a "straightforward" design of
a pipelined CPU and use this design to understand
the operation of a pipelined CPU
- We will will look at how each type of assembler instruction
is executed by the pipelined CPU
- After understanding the operation of the "basic" pipelined CPU,
I will show you a number of problems (hazards)
in the "straightforward" design....
Each of the identified problem will dealed with (this is how "engineers" operate :-))
- There are 5 pipeline stages in the basic pipelined CPU design
- The yellow rectangles are Instruction Registers
for the various pipeline stages
Because the pipelined CPU is executing multiple instructions at once, there are multiple Instruction Registers....
- The gold rectangles are various memory elements
(i.e., the special and general purpose registers).
NOTE: All registers (including Instruction Registers) are constructed with D-flipflops (very short write time - this is necessary to isolate the computation that is going on inside the various pipeline stages)
- The pinkish rectangles are multiplexors or decoders (C-bus)
that are used to select inputs or registers
(we have covered this thoroughly in the non-pipelined CPU and
the same principles and concepts did not (and will not)
change in the discussion of the pipelined CPU).
- The green rectangles are computational circuits (adder, ALU, AND)
- again, there is no difference between adder, ALU circuits
in a non-pipelined and a pipelined CPU.
- The blue rectangle is a branch decision logic circuitry
that make branch decisions (it is similar to
the Branch Logic control circuit discussed in this webpage:
click here )
- Pipelined CPU will increase the execution speed of
instructions.
- As you know, the main memory is 5 - 50 slower than the CPU
(in the time that it take the main memory to fetch one
instruction, the CPU would have executed 5 - 50 instructions....)
- Clearly, using only main memory,
it does not worth the trouble to make a pipelined CPU
(the system will run as fast as the slowest component)
- For now, you must just assume we have very fast memory -
the memory is as fast as the CPU.
I.e., the memory can return the instruction within 1 CPU cycle
- Later we will see cache technique that make main memory "appear" to be very speedy
- There is one clock signal and this clock signal
is not split - so forget about the 4-phase clock
- All registers are tied to this one clock signal, so
all registers (consisting of D-flipflops) are updated once
per clock period.
- However, you should remember that
upto 1 registers of the General Purpose Registers
are updated at once.
- Because the every register must be tied to the clock signal,
due to its simplicity and space (i.e., neatness) limitation,
the clock signal is left out....
- To help make things more concrete, I have designed a simple
assembler instruction format
- which is somewhat based on the SPARC instruction format -
to help you envision the pipeline operation:
- Every assembler instruction is encoded in 16 bits
- The left most bit indicates a load instruction:
- Load the data from memory location R0 + R1 into register R2 (R2 := Memory[R0+R1])
- Another variant of the load instruction is with a constant offset:
- Load the data from memory location R0 + 1 into register R2 (R2 := Memory[R0+1])
- IF stage is the Instruction Fetch stage
- Purpose:
- Fetch next instruction
- Operation:
- At the start of the cycle: send PC onto the Address Bus
- ....Memory will return the assembler instruction on the Databus
- At the end of the clock period: update PC either with:
- PC+4 (instruction following the current instruction)
- or Branch location (from the MEM stage) - in this case, the CPU will make a branch.
- The instruction from memory is stored in the IR of the ID stage
- ID stage is the Instruction Decode stage
- Purpose:
- Fetch all possible operands to prepare for the execution of the (assembler) instruction
- The ID stage does not need know what type of instruction is in the IR of the ID stage
- The ID stage will fetch the operands for every possible instruction...
- Operation:
- Copy the PC register from IF stage into PC1 register (PC1 used in branch instructions)
- Use src1 field in IR(ID) to select a register and store the value in the A register - this value may be used as the first source operand of the ALU
- Use src2 field in IR(ID) to select a register and store the value in the B register - this value may be used as the second source operand of the ALU
- Use dest field in IR(ID) to select a register and store the value in the D register - this value may be used as the store value in a store (write) operation
- Use IR(ID) in an AND operation to extract the constant embedded in the instruction and store the constant operand in the IR1 register
We will examine the 3 types of instruction more closer later and you can verify that the ID stage indeed has now obtain every possible operands for every possible assembler instruction.
- EX stage is the Instruction Execution stage
- Purpose:
- Perform the operation in the assembler instruction
- Operation:
- Use the type of instruction to select
between the PC1 and A input:
- If the instruction is a branch instruction, select PC1 as input 1 of the ALU.
- For all other types of instruction (ALU, load or store) select register A as input 1 of the ALU.
- Use the operand type of instruction to select
between the B and IR1 input:
- If the instruction in IR(EX) specifies a constant operand (e.g., "ADD R1, 5, R2", the operand 5 is a constant), then select IR1 as input 2 of the ALU.
- Otherwise, select B as input 2 of the ALU.
- If the instruction is an ALU instruction,
then the ALU opcode portion of the instruction
to select the operation of the ALU
Otherwise (instruction is load, store or branch), select the ADD function
- Result of the ALU is stored in registers ALUo (ALU output)
and DMAR (Data Memory Address Register)
NOTE: Both DMAR and PC (in IF stage) is tied to the address bus. So we must use tri-state-buffers with these registers to prevent burn-out.
- Value of the B-register is copied into SMDR (Store Memory Data Register) to prepare for the store operation.
- Use the type of instruction to select
between the PC1 and A input:
- MEM stage is the Memory Instruction execution stage
- Purpose:
- Mainly to execute memory access instruction (load and store)
- Also execute branch instructions...
- Load instruction execution:
- Prevent the IF stage from doing its usual operation.
- At the start of the CPU cycle, send value in DMAR out onto the Address Bus (that's why the MEM stage must prevent the IF stage from operating - you can't send 2 addresses on the address bus at the same time)
- ....Memory will return the requested content on the Databus
- At the end of the clock period: load data bus data into LMDR
- Store instruction execution:
- Prevent the IF stage from doing its usual operation.
- At the start of the CPU cycle, send value in DMAR out onto the Address Bus and send the value in SMDR out onto the Databus
- ....Memory will make the requested update....
- At the end of the clock period: do nothing (CPU's job is done)
- Branch instruction execution:
- Use condition code in IR(MEM) and NZVC flags from PSR
to determine the selection signal
Output select=1 if condition for branching has been met, and output select=0 otherwise.
If you follow the connection of the ALUo register to the IF stage, you can see that PC will be updated with the value in the ALUo register when select=1.
- Use condition code in IR(MEM) and NZVC flags from PSR
to determine the selection signal
- The WB Stage
- WB stage is the Write Back stage
- Purpose:
- Store results from ALU and Load instructions in registers
- Operation:
- Use the Load instruction bit in the assembler instruction
(left most bit of assembler instruction)
to control the selection of the MUX
If Load instruction bit = 1, select LMDR register for C-bus output, and otherwise, select ALUo1 as C-bus output.
- Use the Dest field in the assembler instruction
to select a register
- Allow the register to be written only when C-enable = 1
- Use the Load instruction bit in the assembler instruction
(left most bit of assembler instruction)
to control the selection of the MUX
- WB stage is the Write Back stage