- The branch instruction is encoded differently because branch
instructions do not use register operands
- The following is the encoding format for branch instructions:
Br Cond ------ LD ST BRA Opcode <-------------- Offset -------------------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 1 | x | x | y | y | y | y | y | y | y | y | y | y | y | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
- The two bit field "xx" contains the branch condition code.
The branch condition is encoded as our good old (simple) non-pipelined CPU:
0 0 = (not used) 0 1 = Branch on Negative 1 0 = Branch on Zero 1 1 = Always Branch
- The 11 bits field "yyyyyyyyyyy" contains the offset
from the current program location
(which is given by the value in the PC)
The offset (a sign binary number) is used to compute the final branch destination address:
- The reason for relative offset encoding is efficiency:
- An address would require 32 bits to encode
- But most branch instructions are used to implement
if and while
statements. The target address in these cases
is not very far away from the current program location
so the offset can usually be encoding using a 16 bit offset.
- That's a 50% saving....
- An address would require 32 bits to encode
- The BRA LABEL (where LABEL is 10 "bytes" away from
the current instruction) is encoded as follows:
Br Cond ------ LD ST BRA Opcode <-------------- Offset -------------------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ^ ^ | | +-------------------------------------------+ offset = 10
- The BLT LABEL (where LABEL is 10 "bytes" away from
the current instruction) is encoded as follows:
Br Cond ------ LD ST BRA Opcode <-------------- Offset -------------------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ^ ^ | | +-------------------------------------------+ offset = 10
- At start of the CPU cycle, the IF stage sends out PC
- At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (BRA LABEL)
- The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)
- At start of the CPU cycle, the ID stage sends out selection
signal that selects value from registers onto the A, B and D
buses....
- At end of the CPU cycle, registers A, B and D is updated with some
register value (we don't care what values they are, because
the registers will not be used)
At end of the CPU cycle, registers PC1 is updated with the value in PC and IR1 register is updated with the value 0000000001010 (= 4) which is the offset in the branch instruction (these are the values that matter)
Incidently, we need a different mask pattern to extract the branch offset. The following circuit can do the job:
- Also, at the end of the CPU cycle, the instruction (BRA LABEL) is
moved into IR(EX) and a new instruction is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)
- At start of the CPU cycle, the branch instruction bit will make the EX stage selects the value from PC1 as first operand IR1 as the second operand for the ALU.
- We must (can can) make sure that the ALU will always add
the inputs when the instruction in the IR(EX) is a branch instruction.
- At end of the CPU cycle, ALUo and DMAR registers is updated with
the value PC+Offset.
Notice that this is the DESTINATION
(target) location of the branch instruction !!!
Also, SMDR register will be updated with the value R3 (but R3 will not be used - see next step).
Clearly, fetching values into A, B and D registers were harmless....
- Also, at the end of the CPU cycle, the instruction (BRA LABEL) is
moved into IR(MEM) and a new instruction is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)
- The MEM stage of the basic pipelined CPU will execute the
branch instruction.
If the branch is taken, the select hardware in the MEM stage will send out a control signal to the MUX in the IF to direct the ALUo output into PC.
If the branch is not taken, the select hardware will pick PC+4....
In this case (Branch Always), the ALUo value will be sent to the input of the PC at the start of the 4th step.
- At end of the CPU cycle, the PC register is updated with
the value PC+Offset which is equal to the address "LABEL"
in the branch instruction (the assembler will calculate the offset
for you).
Also, at the end of the CPU cycle, the register ALUo1 is updated with PC+Offset. But as you will see, this value will not be used and no harm will be done.
- And at the end of the CPU cycle, the value R3 in SMDR register
is discarded (SMDR register is
only used in a STORE instruction - see later)
- Also, at the end of the CPU cycle, the instruction (BRA LABEL) is
moved into IR(WB) and a new instruction is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the 4th
CPU cycle (and the start of the 5th cycle)
- Notice that PC has now been updated and the next instruction fetched will be the instruction at the label "LABEL", i.e., the program has "finally" made the branch...
- We must make sure that no register is updated by a branch instruction in the WB stage (because branch instructions do not update registers....)
- This can be accomplished by having using the branch instruction bit
in the C-enable decision cicuit:
C-enable sent to registers = C-enable AND (NOT branch) - At the end of the CPU cycle, the instruction (BRA LABEL) is
discarded and a new instruction is fetched into IR(ID)
- Notice that THREE instructions following the BRA instruction has been fetched and will be executed !