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Removing the dummy "NOP" instructions

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• Removing the NOP instruction after an UNCONDITIONAL branch instruction
  • Behavior of an unconditional branch instruction:

    Program with an unconditional branch: s1 s2 s3 bra Label nop s4 s5 .... Label: t1 t2 .... Executed instructions: s1 s2 s3 bra Label nop t1 t2 Observation: The unconditional branch instruction does not need to test flags s3 is always executed

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  • How to remove the dummy NOP instruction after an unconditional branch:

    Move the prior instruction (s3) into the delay slot --- replacing the NOP instruction

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  • Example:

    Program with an unconditional branch: s1 s2 bra Label s3 s4 s5 .... Label: t1 t2 .... Executed instructions: s1 s2 bra Label s3 t1 t2 Observation: We executed the same serie of instructions and in the same order: s1 s2 s3 bra Label (does not affect any register) nop (does not affect any register) t1 t2 So the execution will produce the same outcome !!!

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• Studying the behavior of a CONDITIONAL branch instruction
  • Behavior of an conditional branch instruction:

    Program with a conditional branch: s1 s2 s3 cmp ... bcc Label nop s4 s5 .... Label: t1 t2 .... Executed instructions when branch taken: s1 s2 s3 cmp ... bcc Label nop t1 t2 Executed instructions when branch not taken: s1 s2 s3 cmp ... bcc Label nop s4 s5 Observation: The conditional branch instruction needs to test the flags We cannot move the CMP ... instruction after the conditional branch

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• Annulling branch instruction
  • SPARC has an annulling version of each branch instruction

  • Effect:

    When the branch instruction fails to branch, the instruction in the delay slot is annulled (voided, i.e., replaced by a NOP instruction)

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• Removing the NOP instruction after an CONDITIONAL branch instruction
  • Behavior of an conditional branch instruction:

    Program with a conditional branch: s1 s2 s3 cmp ... bcc Label nop s4 s5 .... Label: t1 t2 .... Same program, without a NOP instruction: s1 s2 s3 cmp ... bcc,a Label ! annulling version t1 s4 s5 .... Label: t2 .... Executed instructions when branch taken: s1 s2 s3 cmp ... bcc,a Label t1 t2 Same instructions and in same order executed as in the original program: s1 s2 s3 cmp ... bcc Label nop t1 t2 Executed instructions when branch not taken: s1 s2 s3 cmp ... bcc,a Label t1 fails, to branch ==> ANNULLED !!! s4 s5 Again, it's the same instructions and order as in the original program: s1 s2 s3 cmp ... bcc Label nop s4 s5 Observation: In both cases, the same serie of instructions are executed in the same order Both programs are equivalent