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Speedup Achieved through Pipelining

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• Achieving Speedup
  • Speedup (speedier execution) is achieved by executing multiple instructions simulataneously

  • Consider the execution of the following sequence of ALU instructions by the basic pipelined CPU:

       ADD R2, R3, R1
       ADD R4, R5, R1
       ADD R6, R7, R1
       ADD R8, R9, R1
       ...
    

  • The following sequence of figures shows how the Pipelined CPU can process multiple instructions simultaneously...

• CPU Cycle 1

  • At start of the CPU cycle, the IF stage sends out PC
  • At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (ADD R2, R3, R1)

    

  • The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)

• CPU Cylce 2
  • At start of the CPU cycle, the ID stage sends out selection signal that selects values from R2 and R3
  • At end of the CPU cycle, A register is updated with R2 = 11, B register is updated with R3= 9.
  • Also, at the end of the CPU cycle, the instruction (ADD R2, R3, R1) is moved into IR(EX) and instruction ADD R4, R5, R1 is fetched into IR(ID)

    

  • The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)

• CPU Cycle 3
  • At start of the CPU cycle, the EX stage selects values from R2 and R3 for the ALU, use the ALU opcode to make ALU add the input values

    Also, at start of the CPU cycle, the ID stage selects R4 and R5 to be copied into the A and B registers.

  • At end of the CPU cycle, ALUo and DMAR registers is updated with the value R1+R2 = 20

    Also, at the end of the CPU cycle, A is updated to R4 and B is updated to R5.

    Also, at the end of the CPU cycle, the instruction (ADD R1, R2, R3) is moved into IR(MEM), ADD R4, R5, R1 is moved into IR(EX) and instruction ADD R6, R7, R1 is fetched into IR(ID)

    

  • The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)

• CPU Cycle 4
  • At start of the CPU cycle, the MEM stage's ALUo1 register will start to receive the output of ADD R2, R3, R1.

  • Also at start of the CPU cycle, the EX stage selects values from R4 and R5 for the ALU, use the ALU opcode to make ALU add the input values

    Also, at start of the CPU cycle, the ID stage selects R6 and R7 to be copied into the A and B registers.

  • At end of the CPU cycle, ALUo1 in MEM stage is updated with the value R2+R3 = 20

  • Also, at end of the CPU cycle, ALUo and DMAR registers is updated with the value R4+R5 = 9

    Also, at the end of the CPU cycle, A is updated to R6 and B is updated to R7.

    Also, at the end of the CPU cycle, the instruction (ADD R1, R2, R3) is moved into IR(WB), ADD R4, R5, R1 is moved into IR(MEM), instruction ADD R6, R7, R1 is moved into IR(EX) and instruction ADD R8, R9, R1 is fetched into IR(ID)

    

  • The picture above depicts the content of the CPU at end of the 4th CPU cycle (and the start of the 4th cycle)

• You can clearly see that R1 will next be update with 20 (= R2+R3), and then with 9 (= R4+R5), and so on.

  So the execution of every instruction will be correct even these instructions are processed simultaneously !!!

  Well, not quite... we will find some problems in the basic pipelined CPU later....

  But before we pick on the basic pipelined CPU, let's look at how the basic pipelined CPU execute the other types of instructions...

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• Demo: click here