---

Executing a Store instruction

---

We now examine in detail how the basic pipeline CPU executes the store instruction.

• Store instruction format
  • Our little toy pipelined CPU will also be able to support 2 types of store instructions:
    • ST R3, [R1 + R2]: store the value in register R3 to memory at address (location) given by R1+R2
    • ST R3, [R1 + N]: store the value in register R3 to memory at address (location) given by R1+N (N is a constant)

• Store Instruction Encoding
  • Example 1: ST R3, [R1 + R2] (Memory[R1 + R2] := R3)

    The instruction is encoded as follows:

    		Br Cond
    		------
       LD  ST  BRA  Opcode  Im Cen <-- Dest -> <- Src1 --> <-- Src2 ->
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    

    Notice that the Cen (C-enable) bit in the store instruction is always set to 0 (we are NOT writing to a register, but to memory !)

  • Example 2: ST R3, [R1 + 2] (Memory[R1 + 2] := R3)

    The instruction is encoded as follows:

    		Br Cond
    		------
       LD  ST  BRA  Opcode  Im Cen <-- Dest -> <- Src1 --> <-- Src2 ->
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    

• Step 1: Fetch

  • At start of the CPU cycle, the IF stage sends out PC
  • At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (ST R3, [R1+R2])

    

  • The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)

• Step 2: Decode (fetch operands)
  • At start of the CPU cycle, the ID stage sends out selection signal that selects values from R1 (on A bus), R2 (on B bus) and R3 (on D bus).
  • At end of the CPU cycle, A register is updated with R1, B register is updated with R2 and D register is updated with R3.
  • Now R1 and R2 will be used to form the address (by adding them together) and the value of R3 will be sent on the data bus to update the selected memory location....
  • Also, at the end of the CPU cycle, the instruction (ST R3, [R1+R2]) is moved into IR(EX) and a new instruction is fetched into IR(ID)

    

  • The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle) - notice that the address (R1 + R2) has not been formed yet... it will be computed right now....

• Step 3: Execute (compute)
  • At start of the CPU cycle, the EX stage selects values from R1 and R2 for the ALU, use the ALU opcode to make ALU add the input values

  • At end of the CPU cycle, ALUo and DMAR registers is updated with the value R1+R2 (the address) and the SMDR register is updated with the value R3 (the store data)
  • Also, at the end of the CPU cycle, the instruction (ST R3, [R1+R2]) is moved into IR(MEM) and a new instruction is fetched into IR(ID)

    

  • The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)
  • Notice that the address (R1+R2) is connected to the address bus and the data (R3) is connected to the databus !!!

• Step 4: Memory Access or Branch
  • The MEM stage uses the system bus to access the memory to perform the store operation
  • As the case in the load operation, the IF stage also wants to use the system bus to fetch the next instruction
  • The MEM and IF stage cannot share the system bus.
  • We must assign priority of its use: give higher priority to the later pipeline stage (in this case: MEM stage)

  • Conclusion: the IF stage must STALL during step 4.

    Stall the IF stage when the instruction in the MEM stage is a STORE instruction (this fact can be recognized from the ST bit in the instruction)

    

  • Also: the STORE instruction in the MEM stage will certanly not have any effect on the execution of the instructions in the ID and EX stages. So the ID and EX stages are not required to be stalled.

  • There is the same caveat that need to be taken care of in the LOAD instruction:
    • The ID stage and EX stage can (and will) keep moving...
    • Normally, the next instruction (from memory) is fetched into IR(ID)...
    • Now that the IF stage is stalled (not working), there is no "next" instruction...
    • Yet, we must put some instruction in IR(ID)...
    • Solution: insert a "harmless" instruction NOP (you have seen how to do that)

  • At end of the CPU cycle, ALUo1 registers is updated with the value R1+R2
  • Also, at the end of the CPU cycle, the instruction (ST R3, [R1+R2]) is moved into IR(WB) and the NOP instruction is fetched into IR(ID)

    

  • The picture above depicts the content of the CPU at end of the 4rd CPU cycle (and the start of the 5th cycle)

• Step 5: Update register
  • Although the destination register field is R3, but C-enable is ZERO ! So, although R3 is selected, no register is updated by the STORE instruction.
  • This is correct, because the STORE instruction updates a memory location, and not a register.

  • At the end of the CPU cycle, the instruction (ST R3, [R1+R2]) is discarded and a new instruction is fetched into IR(ID)
  • Notice that the NOP instruction will proceed through the pipe, since it does no harm, its only effect is that the CPU "run less fast"...