/*	********************
	Advanced Pipelined CPU
	by Aaron Bush
	********************
*/

/* --------------------
	R1 = 123
	R2 = 11
	R3 = 9
	R4 = 1
	R5 = 8
	R6 = 0
	R7 = 2

	goto LABEL
	R2 += R1
	R3 += R1
	R4 += R1
	R5 += R1
	R6 += R1
	R7 += R1
LABEL:
	--------------------
*/
Define Memory MReq Read Addr[15-0] DataIn[15-0] | DataOut[15-0];
	Rom64x16 aa-ea Addr[5-0] ZERO RomOut[15-0]
		2683	4619	6665	8705	10760	14850	0		0
		0		0		49175	4113	6169	8225	10281	12337
		14393	0		0		0		0		0		0		0
		0		0		0		0		0		0		0		0
		0		0		0		0		0		0		0		0
		0		0		0		0		0		0		0		0
		0		0		0		0		0		0		0		0
		0		0		0		0		0		0		0		0;
	Ram64x8 ad-ed DataIn[15-8] Addr[5-0] RW enRAM RamOut[15-8];
	Ram64x8 af-ef DataIn[7-0] Addr[5-0] RW enRAM RamOut[7-0];
	And aa MReq Read enTriLink;
	MemAddr1 fa MReq Read Addr[6] | enTriROM;
	MemAddr2 fd MReq Read Addr[6] | RW enRAM enTriRAM;
	Tri-state-buffer ab-eb DataIn[15-0] enTriLink | DataOut[15-0];
	Tri-state-buffer ab-eb RomOut[15-0] enTriROM | DataOut[15-0];
	Tri-state-buffer ae-ee RamOut[15-0] enTriRAM | DataOut[15-0];
Endef;

Define MemAddr1 MREQ Read A6 | enTriROM;
	Not aa A6 nA6;
	Nand ba MREQ Read nA6 enTriROM;
Endef;

Define MemAddr2 MREQ Read A6 | RW enRAM enTriRAM;
	Or aa Read RW;
	Nand ba MREQ A6 enRAM;
	Nand ca MREQ Read A6 enTriRAM;
Endef;

/* --- Link3 ---
	Connects 3-bit input to the 3-bit output
*/
Define Link3 in[2-0] | out[2-0];
	Or aa in[2] out[2];
	Or aa in[1] out[1];
	Or aa in[0] out[0];
Endef;

/* --- Link16 ---
	Connects 16-bit input to the 16-bit output
*/
Define Link16 in[15-0] | out[15-0];
	Or aa in[15] out[15];
	Or aa in[14] out[14];
	Or aa in[13] out[13];
	Or aa in[12] out[12];
	Or aa in[11] out[11];
	Or aa in[10] out[10];
	Or aa in[9] out[9];
	Or aa in[8] out[8];
	Or aa in[7] out[7];
	Or aa in[6] out[6];
	Or aa in[5] out[5];
	Or aa in[4] out[4];
	Or aa in[3] out[3];
	Or aa in[2] out[2];
	Or aa in[1] out[1];
	Or aa in[0] out[0];
Endef;

/* --- Decoder2x4 ---
	2bit binary decoder with positive logic
*/
Define Decoder2x4 in[1-0] | out[3-0];
	Not aa in[1] noti1;
	Not aa in[0] noti0;
	And aa noti1 noti0 out[0];
	And aa noti1 in[0] out[1];
	And aa in[1] noti0 out[2];
	And aa in[1] in[0] out[3];
Endef;

/* --- Decoder3x8 ---
	3bit binary decoder with positive logic
*/
Define Decoder3x8 in[2-0] | out[7-0];
	Not aa in[2] noti2;
	Not aa in[1] noti1;
	Not aa in[0] noti0;
	And aa noti2 noti1 noti0 out[0];
	And aa noti2 noti1 in[0] out[1];
	And aa noti2 in[1] noti0 out[2];
	And aa noti2 in[1] in[0] out[3];
	And aa in[2] noti1 noti0 out[4];
	And aa in[2] noti1 in[0] out[5];
	And aa in[2] in[1] noti0 out[6];
	And aa in[2] in[1] in[0] out[7];
Endef;

/* --- MyDelay ---
	This puts a delay on a 16-bit signal
*/
Define MyDelay in[15-0] | out[15-0];
	Cable aa in[15] out[15] 50;
	Cable aa in[14] out[14] 50;
	Cable aa in[13] out[13] 50;
	Cable aa in[12] out[12] 50;
	Cable aa in[11] out[11] 50;
	Cable aa in[10] out[10] 50;
	Cable aa in[9] out[9] 50;
	Cable aa in[8] out[8] 50;
	Cable aa in[7] out[7] 50;
	Cable aa in[6] out[6] 50;
	Cable aa in[5] out[5] 50;
	Cable aa in[4] out[4] 50;
	Cable aa in[3] out[3] 50;
	Cable aa in[2] out[2] 50;
	Cable aa in[1] out[1] 50;
	Cable aa in[0] out[0] 50;
Endef;

/* --- Reg16 ---
	Resetable, 16bit, edge-active register with positive logic
*/
Define Reg16 in[15-0] load reset | out[15-0];
	Not aa reset rset;
	Dff aa ONE in[15] load rset out[15] x15;
	Dff aa ONE in[14] load rset out[14] x14;
	Dff aa ONE in[13] load rset out[13] x13;
	Dff aa ONE in[12] load rset out[12] x12;
	Dff aa ONE in[11] load rset out[11] x11;
	Dff aa ONE in[10] load rset out[10] x10;
	Dff aa ONE in[9] load rset out[9] x9;
	Dff aa ONE in[8] load rset out[8] x8;
	Dff aa ONE in[7] load rset out[7] x7;
	Dff aa ONE in[6] load rset out[6] x6;
	Dff aa ONE in[5] load rset out[5] x5;
	Dff aa ONE in[4] load rset out[4] x4;
	Dff aa ONE in[3] load rset out[3] x3;
	Dff aa ONE in[2] load rset out[2] x2;
	Dff aa ONE in[1] load rset out[1] x1;
	Dff aa ONE in[0] load rset out[0] x0;
Endef;

/* --- Registers ---
	The 8x16bit registers in the basic pipelined CPU
	Reg0 is a constant equal to zero
*/
Define Registers reset clock load select[2-0] data[15-0] | Reg7[15-0] Reg6[15-0] Reg5[15-0] Reg4[15-0] Reg3[15-0] Reg2[15-0] Reg1[15-0] Reg0[15-0];
	Or aa ZERO Reg0[15];
	Or aa ZERO Reg0[14];
	Or aa ZERO Reg0[13];
	Or aa ZERO Reg0[12];
	Or aa ZERO Reg0[11];
	Or aa ZERO Reg0[10];
	Or aa ZERO Reg0[9];
	Or aa ZERO Reg0[8];
	Or aa ZERO Reg0[7];
	Or aa ZERO Reg0[6];
	Or aa ZERO Reg0[5];
	Or aa ZERO Reg0[4];
	Or aa ZERO Reg0[3];
	Or aa ZERO Reg0[2];
	Or aa ZERO Reg0[1];
	Or aa ZERO Reg0[0];
	Decoder3x8 aa select[2-0] | sel[7-0];
	And aa clock load sel[7] write[7];
	And aa clock load sel[6] write[6];
	And aa clock load sel[5] write[5];
	And aa clock load sel[4] write[4];
	And aa clock load sel[3] write[3];
	And aa clock load sel[2] write[2];
	And aa clock load sel[1] write[1];
	Reg16 aa data[15-0] write[7] reset | Reg7[15-0];
	Reg16 aa data[15-0] write[6] reset | Reg6[15-0];
	Reg16 aa data[15-0] write[5] reset | Reg5[15-0];
	Reg16 aa data[15-0] write[4] reset | Reg4[15-0];
	Reg16 aa data[15-0] write[3] reset | Reg3[15-0];
	Reg16 aa data[15-0] write[2] reset | Reg2[15-0];
	Reg16 aa data[15-0] write[1] reset | Reg1[15-0];
Endef;

/* --- Adder ---
	1bit adder circuit with carry in/out
*/
Define Adder cin a b | cout sum;
	Xor aa a b x;
	Xor aa x cin sum;
	And aa a b y;
	And aa cin x z;
	Or aa y z cout;
Endef;

/* --- Subtracter ---
	1bit subtracter circuit with borrow in/out
*/
Define Subtracter cin a b | cout s;
	Xor aa a b tmp;
	Xor aa tmp cin s;
	Not aa a na;
	Or aa b cin borc;
	And aa na borc pos[0];
	And aa a b cin pos[1];
	Or aa pos[0-1] cout;
Endef;

/* --- ALUComponent ---
	ALU component that gives a 1bit result for 2-1bit operands
*/
Define ALUComponent cin a b c[1-0] | cout s;
	Adder aa cin a b | carry add;
	Subtracter aa cin a b | borrow subtract;
	And aa a b and;
	Or aa a b or;
	Mux2 aa borrow carry c[0] cout;
	Mux4 aa or and subtract add c[1-0] s;
Endef;

/* --- ALU ---
	The complete 16bit ALU
		00 = ADD
		01 = SUBTRACT
		10 = AND
		11 = OR
*/
Define ALU a[15-0] b[15-0] c[2-0] | out[15-0] N Z;
	ALUComponent aa ZERO a[0] b[0] c[1-0] | carry[0] s[0];
	ALUComponent aa carry[0] a[1] b[1] c[1-0] | carry[1] s[1];
	ALUComponent aa carry[1] a[2] b[2] c[1-0] | carry[2] s[2];
	ALUComponent aa carry[2] a[3] b[3] c[1-0] | carry[3] s[3];
	ALUComponent aa carry[3] a[4] b[4] c[1-0] | carry[4] s[4];
	ALUComponent aa carry[4] a[5] b[5] c[1-0] | carry[5] s[5];
	ALUComponent aa carry[5] a[6] b[6] c[1-0] | carry[6] s[6];
	ALUComponent aa carry[6] a[7] b[7] c[1-0] | carry[7] s[7];
	ALUComponent aa carry[7] a[8] b[8] c[1-0] | carry[8] s[8];
	ALUComponent aa carry[8] a[9] b[9] c[1-0] | carry[9] s[9];
	ALUComponent aa carry[9] a[10] b[10] c[1-0] | carry[10] s[10];
	ALUComponent aa carry[10] a[11] b[11] c[1-0] | carry[11] s[11];
	ALUComponent aa carry[11] a[12] b[12] c[1-0] | carry[12] s[12];
	ALUComponent aa carry[12] a[13] b[13] c[1-0] | carry[13] s[13];
	ALUComponent aa carry[13] a[14] b[14] c[1-0] | carry[14] s[14];
	ALUComponent aa carry[14] a[15] b[15] c[1-0] | carry[15] s[15];
	Mux-mxn aa b[7-0] ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO a[15-8] b[7-0] c[1] | hilo[15-0];
	Mux-mxn aa hilo[15-0] s[15-0] c[2] | out[15-0];
	Or aa out[15] N;
	Nor aa out[15-0] Z;
Endef;

/* --- Plus ---
	Adds two 16bit numbers
*/
Define Plus a[15-0] b[15-0] | out[15-0];
	Adder aa ZERO a[0] b[0] | c[0] out[0];
	Adder aa c[0] a[1] b[1] | c[1] out[1];
	Adder aa c[1] a[2] b[2] | c[2] out[2];
	Adder aa c[2] a[3] b[3] | c[3] out[3];
	Adder aa c[3] a[4] b[4] | c[4] out[4];
	Adder aa c[4] a[5] b[5] | c[5] out[5];
	Adder aa c[5] a[6] b[6] | c[6] out[6];
	Adder aa c[6] a[7] b[7] | c[7] out[7];
	Adder aa c[7] a[8] b[8] | c[8] out[8];
	Adder aa c[8] a[9] b[9] | c[9] out[9];
	Adder aa c[9] a[10] b[10] | c[10] out[10];
	Adder aa c[10] a[11] b[11] | c[11] out[11];
	Adder aa c[11] a[12] b[12] | c[12] out[12];
	Adder aa c[12] a[13] b[13] | c[13] out[13];
	Adder aa c[13] a[14] b[14] | c[14] out[14];
	Adder aa c[14] a[15] b[15] | c[15] out[15];
Endef;

/* --- Equals ---
	Tests if two 3bit numbers are equal
*/
Define Equals a[2-0] b[2-0] | equals;
	Xnor aa a[2] b[2] e[2];
	Xnor aa a[1] b[1] e[1];
	Xnor aa a[0] b[0] e[0];
	And aa e[2-0] equals;
Endef;

/* --- IR ---
	16bit instruction register used at each stage of pipelined CPU
*/
Define IR reset clock stall in[15-0] | out[15-0];
	Not aa clock _clock;
	Or aa _clock stall enableIR;
	Reg16 ca-cb in[15-0] enableIR reset | out[15-0];
Endef;

/* --- InstructionDecoder ---
	Decoder that determines what type of instruction is decoded
*/
Define InstructionDecoder IR[15-0] | alu ld st branch sethi setlo hilo psr immediate;
	Decoder2x4 aa IR[15-14] | branch st ld alu;
	And aa alu IR[10] psr;
	Or aa IR[6] immediate;
	Decoder3x8 aa IR[9-7] | hi1 hi2 lo1 lo2 or and subtract add;
	Or aa hi1 hi2 _sethi;
	Or aa lo1 lo2 _setlo;
	And aa alu _sethi sethi;
	And aa alu _setlo setlo;
	Or aa sethi setlo hilo;
Endef;

/* --- ALU1 ---
	Determines which register to use as operand 1 for the ALU
*/
Define ALU1 PC1[15-0] A[15-0] alu3[15-0] branch setlo reg[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] WBD[3-0] LMDR[15-0] | out[15-0];
	GP_DataForwCircuit aa reg[2-0] Tag2[3-0] FR2[15-0] A[15-0] | a[15-0];
	GP_DataForwCircuit aa reg[2-0] Tag1[3-0] FR1[15-0] a[15-0] | b[15-0];
	GP_DataForwCircuit aa reg[2-0] WBD[3-0] LMDR[15-0] b[15-0] | c[15-0];
	Mux-mxn aa alu3[15-0] c[15-0] setlo | d[15-0];
	Mux-mxn ab PC1[15-0] d[15-0] branch | out[15-0];
Endef;

/* --- ALU2 ---
	Determines which register to use as operand 2 for the ALU
*/
Define ALU2 B[15-0] IR1[15-0] branch hilo immediate reg[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] WBD[3-0] LMDR[15-0] | out[15-0];
	GP_DataForwCircuit aa reg[2-0] Tag2[3-0] FR2[15-0] B[15-0] | a[15-0];
	GP_DataForwCircuit aa reg[2-0] Tag1[3-0] FR1[15-0] a[15-0] | b[15-0];
	GP_DataForwCircuit aa reg[2-0] WBD[3-0] LMDR[15-0] b[15-0] | c[15-0];
	Or aa branch hilo immediate condition;
	Mux-mxn ab IR1[15-0] c[15-0] condition | out[15-0];
Endef;

/* --- ALU3 ---
	Determines the right value for D (used in setlo and st operations)
*/
Define ALU3 D[15-0] reg[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] WBD[3-0] LMDR[15-0] | out[15-0];
	GP_DataForwCircuit aa reg[2-0] Tag2[3-0] FR2[15-0] D[15-0] | a[15-0];
	GP_DataForwCircuit aa reg[2-0] Tag1[3-0] FR1[15-0] a[15-0] | b[15-0];
	GP_DataForwCircuit aa reg[2-0] WBD[3-0] LMDR[15-0] b[15-0] | out[15-0];
Endef;

/* --- IF ---
	Instruction Fetch

	Rising edge:
		Request the next instruction from memory at address PC

	Falling edge:
		Copy PC to PCtmp
		Update PC with either PC+1 or a branch address
		Write the fetched instruction to IR(ID)
*/
Define IF reset clock stall branch branchAddr[15-0] dataIn[15-0] | memory read addrOut[15-0] PC[15-0] PCtmp[15-0] instruction[15-0];
	Not aa clock _clock;
	Or aa _clock stall update;
	Not aa update memory;
	Or aa ONE read;
	Link16 aa dataIn[15-0] | instruction[15-0];
	Mux-mxn ca-cp branchAddr[15-0] PCPlus1[15-0] branch | NextInstr[15-0];
	Reg16 da-dp NextInstr[15-0] update reset | PC[15-0];
	Plus cq-ds PC[15-0] ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ONE | PCPlus1[15-0];
	Reg16 da-dp PC[15-0] update reset | PCtmp[15-0];
	Tri-state-buffer fa PC[15-0] update | addrOut[15-0];
Endef;

/* --- ID ---
	Instruction Decode

	Falling edge:
		Copy PCtmp to PC1
		Update A from the src1 register in the instruction
		Update B from the src2 register in the instruction
		Update IR1 with the constant for the given instruction
		Update D from the dest register in the instruction
		Pass the instruction on to IR(EX)
*/
Define ID reset clock stall IR[15-0] PCtmp[15-0] src1[15-0] src2[15-0] src3[15-0] | src1_sel[2-0] src2_sel[2-0] src3_sel[2-0] PC1[15-0] A[15-0] B[15-0] IR1[15-0] D[15-0] branch brAddr[15-0];
	InstructionDecoder aa IR[15-0] | alu ld st branch sethi setlo hilo psr immediate;
	Not aa clock _clock;
	Or aa _clock stall update;
	Link3 aa IR[5-3] | src1_sel[2-0];
	Link3 aa IR[2-0] | src2_sel[2-0];
	Link3 aa IR[13-11] | src3_sel[2-0];
	Mux-mxn db-fb ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO IR[7-0] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2] IR[2-0] hilo | inter[15-0];
	Mux-mxn db-fb IR[10] IR[10] IR[10] IR[10] IR[10] IR[10-0] inter[15-0] branch | constant[15-0];
	Reg16 ad PCtmp[15-0] update reset | PC1[15-0];
	Reg16 bd src1[15-0] update reset | A[15-0];
	Reg16 dd src2[15-0] update reset | B[15-0];
	Reg16 ed constant[15-0] update reset | IR1[15-0];
	Reg16 gd src3[15-0] update reset | D[15-0];
	Plus hd PCtmp[15-0] constant[15-0] | brAddr[15-0];
Endef;

/* --- EX ---
	Execution

	Falling edge:
		Update ALUo and DMAR with the output of the ALU
			ALUo is used for ALU, Branch, and SETHI instructions
			DMAR is the address used for LD and ST instructions
		Update SMDR with the value from D
			SMDR is the value that is written in a ST instruction
		Pass the instruction on to IR(MEM)
*/
Define EX reset clock stall IR[15-0] alu1[15-0] alu2[15-0] alu3[15-0] | exBranch exSetlo exHilo exImmediate N Z ALUo[15-0] DMAR[15-0] SMDR[15-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] exSRC1[2-0] exSRC2[2-0] exSRC3[2-0];
	InstructionDecoder aa IR[15-0] | alu ld st exBranch sethi exSetlo exHilo psr exImmediate;
	Not aa psr _psr;
	Or aa clock stall _psr updatePSR;
	Cable aa updatePSR psrSignal 0;
	PSR dd reset psrSignal Ni Zi | N Z;
	Not aa clock _clock;
	Or aa _clock stall update;
	Mux-mxn ab ZERO ZERO ZERO IR[9-7] exBranch | operation[2-0];
	ALU ac alu1[15-0] alu2[15-0] operation[2-0] | alu[15-0] Ni Zi;
	Reg16 ad alu[15-0] update reset | ALUo[15-0];
	Reg16 bd alu[15-0] update reset | DMAR[15-0];
	Reg16 cd alu3[15-0] update reset | SMDR[15-0];
	Equals aa IR[13-11] ZERO ZERO ZERO | regZero;
	Not aa regZero notRegZero;
	And aa alu notRegZero validateFR;
	DataForwRegs aa reset update validateFR IR[13-11] alu[15-0] | Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0];
	Link3 aa IR[5-3] | exSRC1[2-0];
	Link3 aa IR[2-0] | exSRC2[2-0];
	Link3 aa IR[13-11] | exSRC3[2-0];
Endef;

Define DataForwRegs reset update valid reg[2-0] value[15-0] | Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0];
	Not aa reset _reset;
	Dff aa ONE valid update _reset Tag1[3] x13;
	Dff aa ONE reg[2] update _reset Tag1[2] x12;
	Dff aa ONE reg[1] update _reset Tag1[1] x11;
	Dff aa ONE reg[0] update _reset Tag1[0] x10;
	Dff aa ONE Tag1[3] update _reset Tag2[3] x23;
	Dff aa ONE Tag1[2] update _reset Tag2[2] x22;
	Dff aa ONE Tag1[1] update _reset Tag2[1] x21;
	Dff aa ONE Tag1[0] update _reset Tag2[0] x20;
	Reg16 aa value[15-0] update reset | FR1[15-0];
	Reg16 aa FR1[15-0] update reset | FR2[15-0];
Endef;

Define GP_DataForwCircuit reg[2-0] valid tag[2-0] fr[15-0] other[15-0] | out[15-0];
	Equals aa reg[2-0] tag[2-0] | equals;
	And aa valid equals useFR;
	Mux-mxn aa fr[15-0] other[15-0] useFR | out[15-0];
Endef;

/* --- PSR ---
	Memory for the N and Z flags that only updates on a "cc" instruction
*/
Define PSR reset update Ni Zi | N Z;
	Not aa reset rset;
	Dff ba ONE Ni update rset N xN;
	Dff bb ONE Zi update rset Z xZ;
Endef;

/* --- MEM ---
	Memory and Branch

	Rising edge:
		Request that memory perform the LD/ST operation

	Falling edge:
		Update ALUo1 with the value from ALUo
		Update LMDR with the value returned from memory in a LD operation
		Pass the instruction on to IR(WB)
*/
Define MEM reset clock stall IR[15-0] ALUo[15-0] DMAR[15-0] SMDR[15-0] dataIn[15-0] | memory ld ALUo1[15-0] LMDR[15-0] addrOut[15-0] dataOut[15-0];
	InstructionDecoder aa IR[15-0] | alu ld st isBranch sethi setlo hilo psr immediate;
	Not aa clock _clock;
	Not aa stall _stall;
	Or aa _clock stall update;
	Reg16 ad-ae ALUo[15-0] update reset | ALUo1[15-0];
	Or ba ld st memoryAccess;
	Nand ba _stall clock memoryAccess enableTSB;
	Nand ba _stall clock st enableWriteTSB;
	Not da enableTSB memory;
	Tri-state-buffer ea DMAR[15-0] enableTSB | addrOut[15-0];
	Tri-state-buffer fa SMDR[15-0] enableWriteTSB | dataOut[15-0];
	Reg16 dd-de dataIn[15-0] update reset | LMDR[15-0];
Endef;

/* --- BranchDecision
	Based on the branch code and PSR values, determines whether to branch
*/
Define BranchDecision isBranch c[2-0] lt eq | branch;
	Decoder3x8 aa c[2-0] | garbage BGE BGT BLE BLT BNE BEQ BRA;
	Not aa eq ne;
	Or aa lt eq le;
	Not aa le gt;
	Not aa lt ge;
	And aa BEQ eq opt[0];
	And aa BNE ne opt[1];
	And aa BLT lt opt[2];
	And aa BLE le opt[3];
	And aa BGT gt opt[4];
	And aa BGE ge opt[5];
	Or aa BRA opt[0-5] conditionMet;
	And aa conditionMet isBranch branch;
Endef;

/* --- WB ---
	Write Back

	Rising edge:
		Update the dest register on any non-ST/non-Branch instruction
*/
Define WB clock IR[15-0] ALUo1[15-0] LMDR[15-0] | writeRegister regSelect[2-0] registerInput[15-0] validateLMDR;
	InstructionDecoder aa IR[15-0] | alu ld st branch sethi setlo hilo psr immediate;
	Or aa alu ld writeRegister;
	Link3 aa IR[13-11] | regSelect[2-0];
	Mux-mxn ca-da LMDR[15-0] ALUo1[15-0] ld | registerInput[15-0];
	Equals aa IR[13-11] ZERO ZERO ZERO | regZero;
	Not aa regZero notRegZero;
	And aa ld notRegZero validateLMDR;
Endef;

Define Stall_IF ID_stall IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stall;
	InstructionDecoder aa IR_MEM[15-0] | alu ld st branch sethi setlo hilo psr immediate;
	Or ba ID_stall ld st stall;
Endef;

Define Stall_ID EX_stall IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stall;
	Or aa EX_stall stall;
Endef;

Define Stall_EX MEM_stall IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stall;
	InstructionDecoder aa IR_MEM[15-0] | mem_alu mem_ld mem_st mem_branch mem_sethi mem_setlo mem_hilo mem_psr mem_immediate;
	InstructionDecoder aa IR_EX[15-0] | ex_alu ex_ld ex_st ex_branch ex_sethi ex_setlo ex_hilo ex_psr ex_immediate;
	Equals aa IR_EX[5-3] IR_MEM[13-11] | src1Invalid;
	Equals aa IR_EX[2-0] IR_MEM[13-11] | src2Invalid;
	Equals aa IR_EX[13-11] IR_MEM[13-11] | src3Invalid;
	Or aa src1Invalid src2Invalid src12Invalid;
	Or aa ex_alu ex_ld ex_st src12Needed;
	And aa src12Invalid src12Needed src12stall;
	Or aa ex_setlo ex_st src3Needed;
	And aa src3Invalid src3Needed src3stall;
	Or aa src12stall src3stall badSource;
	And aa mem_ld badSource mustStall;
	Or aa MEM_stall mustStall stall;
Endef;

Define Stall_MEM IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stall;
	Or aa ZERO stall;
Endef;

Define AdvancedPipe reset clock DataBusIn[15-0] | memory read AddrBusOut[15-0] DataBusOut[15-0] PC[15-0] PCtmp[15-0] IR_ID[15-0] PC1[15-0] A[15-0] B[15-0] IR1[15-0] D[15-0] IR_EX[15-0] ALUo[15-0] DMAR[15-0] SMDR[15-0] N Z IR_MEM[15-0] ALUo1[15-0] LMDR[15-0] IR_WB[15-0] Reg0[15-0] Reg1[15-0] Reg2[15-0] Reg3[15-0] Reg4[15-0] Reg5[15-0] Reg6[15-0] Reg7[15-0] stallIF stallID stallEX stallMEM branchDecision validateLMDR registerSelect[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0];
	Registers av-dz reset clock writeRegister registerSelect[2-0] registerInput[15-0] | Reg7[15-0] Reg6[15-0] Reg5[15-0] Reg4[15-0] Reg3[15-0] Reg2[15-0] Reg1[15-0] Reg0[15-0];

	Stall_IF ja-jb stallID IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stallIF;
	IF fa-hb reset clock stallIF branchDecision brAddr[15-0] DataBusIn[15-0] | memrq_IF rw_IF aOut[15-0] PC[15-0] PCtmp[15-0] instruction[15-0];
	Mux-mxn "NOP?" ic Reg0[15-0] instruction[15-0] stallIF | IR_ID_in[15-0];
	IR if-ih reset clock stallID IR_ID_in[15-0] | IR_ID[15-0];

	Stall_ID jf-jh stallEX IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stallID;
	ID ff-hh reset clock stallID IR_ID[15-0] PCtmp[15-0] src1[15-0] src2[15-0] src3[15-0] | src1_sel[2-0] src2_sel[2-0] src3_sel[2-0] PC1[15-0] A[15-0] B[15-0] IR1[15-0] D[15-0] isBranch brAddr[15-0];
	Mux-mxn "src1" bg Reg7[15-0] Reg6[15-0] Reg5[15-0] Reg4[15-0] Reg3[15-0] Reg2[15-0] Reg1[15-0] Reg0[15-0] src1_sel[2-0] | src1[15-0];
	Mux-mxn "src2" cg Reg7[15-0] Reg6[15-0] Reg5[15-0] Reg4[15-0] Reg3[15-0] Reg2[15-0] Reg1[15-0] Reg0[15-0] src2_sel[2-0] | src2[15-0];
	Mux-mxn "src3" dg Reg7[15-0] Reg6[15-0] Reg5[15-0] Reg4[15-0] Reg3[15-0] Reg2[15-0] Reg1[15-0] Reg0[15-0] src3_sel[2-0] | src3[15-0];
	Mux-mxn "NOP?" ij Reg0[15-0] IR_ID[15-0] stallID | IR_EX_in[15-0];
	IR il-in reset clock stallEX IR_EX_in[15-0] | IR_EX[15-0];

	Stall_EX jl-jn stallMEM IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stallEX;
	EX fl-hn reset clock stallEX IR_EX[15-0] alu1[15-0] alu2[15-0] alu3[15-0] | exBranch exSetlo exHilo exImmediate N Z ALUo[15-0] DMAR[15-0] SMDR[15-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] exSRC1[2-0] exSRC2[2-0] exSRC3[2-0];
	ALU1 gj PC1[15-0] A[15-0] alu3[15-0] exBranch exSetlo exSRC1[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] validateLMDR registerSelect[2-0] LMDR[15-0] | alu1[15-0];
	ALU2 gj B[15-0] IR1[15-0] exBranch exHilo exImmediate exSRC2[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] validateLMDR registerSelect[2-0] LMDR[15-0] | alu2[15-0];
	ALU3 gj D[15-0] exSRC3[2-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0] validateLMDR registerSelect[2-0] LMDR[15-0] | alu3[15-0];
	Mux-mxn "NOP?" ip Reg0[15-0] IR_EX[15-0] stallEX | IR_MEM_in[15-0];
	IR ir-it reset clock stallMEM IR_MEM_in[15-0] | IR_MEM[15-0];

	Stall_MEM jr-jt IR_ID[15-0] IR_EX[15-0] IR_MEM[15-0] | stallMEM;
	MEM fr-ht reset clock stallMEM IR_MEM[15-0] ALUo[15-0] DMAR[15-0] SMDR[15-0] DataBusIn[15-0] | memrq_MEM rw_MEM ALUo1[15-0] LMDR[15-0] aOut[15-0] dOut[15-0];
	BranchDecision dm isBranch src3_sel[2-0] N Z | branchDecision;
	Mux-mxn "NOP?" iv Reg0[15-0] IR_MEM[15-0] stallMEM | IR_WB_in[15-0];
	IR ix-iz reset clock ZERO IR_WB_in[15-0] | IR_WB[15-0];

	WB fx-hz clock IR_WB[15-0] ALUo1[15-0] LMDR[15-0] | writeRegister registerSelect[2-0] registerInput[15-0] validateLMDR;

	Or ds memrq_IF memrq_MEM memory;
	Mux2 ds rw_MEM rw_IF memrq_MEM read;
	MyDelay ds aOut[15-0] | AddrBusOut[15-0];
	MyDelay ds dOut[15-0] | DataBusOut[15-0];
Endef;

AdvancedPipe la-sj reset clock DataBus[15-0] | memory read AddrBus[15-0] DataWrite[15-0] PC[15-0] PCtmp[15-0] IR_ID[15-0] PC1[15-0] A[15-0] B[15-0] IR1[15-0] D[15-0] IR_EX[15-0] ALUo[15-0] DMAR[15-0] SMDR[15-0] N Z IR_MEM[15-0] ALUo1[15-0] LMDR[15-0] IR_WB[15-0] Reg0[15-0] Reg1[15-0] Reg2[15-0] Reg3[15-0] Reg4[15-0] Reg5[15-0] Reg6[15-0] Reg7[15-0] stallIF stallID stallEX stallMEM branchDecision WBD[3-0] Tag1[3-0] FR1[15-0] Tag2[3-0] FR2[15-0];

Memory ol-sn memory read AddrBus[15-0] DataWrite[15-0] | DataBus[15-0];

Probe "I" aa.aa PC[15];
Probe "F" aa.ab PC[14];
Probe ":" aa.ac PC[13];
Probe aa.ad PC[12];
Probe "P" aa.ae PC[11];
Probe "C" ab.aa PC[10];
Probe ab.ab PC[9];
Probe ab.ac PC[8];
Probe ab.ad PC[7];
Probe ab.ae PC[6];
Probe ac.aa PC[5];
Probe ac.ab PC[4];
Probe ac.ac PC[3];
Probe ac.ad PC[2];
Probe ac.ae PC[1];
Probe ad.aa PC[0];
Switch "0:RST" ad.ac-ae reset ONE;

Probe "I" ba.aa PCtmp[15];
Probe "F" ba.ab PCtmp[14];
Probe ":" ba.ac PCtmp[13];
Probe ba.ad PCtmp[12];
Probe "P" ba.ae PCtmp[11];
Probe "C" bb.aa PCtmp[10];
Probe "t" bb.ab PCtmp[9];
Probe "m" bb.ac PCtmp[8];
Probe "p" bb.ad PCtmp[7];
Probe bb.ae PCtmp[6];
Probe bc.aa PCtmp[5];
Probe bc.ab PCtmp[4];
Probe bc.ac PCtmp[3];
Probe bc.ad PCtmp[2];
Probe bc.ae PCtmp[1];
Probe bd.aa PCtmp[0];
Switch "1:CLK" bd.ac-ae clock ZERO;

Probe "MemRq" ak.aa-ac memory;
Probe "A" ak.ae AddrBus[15];
Probe "d" al.aa AddrBus[14];
Probe "d" al.ab AddrBus[13];
Probe "r" al.ac AddrBus[12];
Probe "e" al.ad AddrBus[11];
Probe "s" al.ae AddrBus[10];
Probe "s" am.aa AddrBus[9];
Probe am.ab AddrBus[8];
Probe "B" am.ac AddrBus[7];
Probe "u" am.ad AddrBus[6];
Probe "s" am.ae AddrBus[5];
Probe an.aa AddrBus[4];
Probe an.ab AddrBus[3];
Probe an.ac AddrBus[2];
Probe an.ad AddrBus[1];
Probe an.ae AddrBus[0];

Probe "R/W" bk.aa-ac read;
Probe "D" bk.ae DataBus[15];
Probe "a" bl.aa DataBus[14];
Probe "t" bl.ab DataBus[13];
Probe "a" bl.ac DataBus[12];
Probe bl.ad DataBus[11];
Probe "B" bl.ae DataBus[10];
Probe "u" bm.aa DataBus[9];
Probe "s" bm.ab DataBus[8];
Probe bm.ac DataBus[7];
Probe bm.ad DataBus[6];
Probe bm.ae DataBus[5];
Probe bn.aa DataBus[4];
Probe bn.ab DataBus[3];
Probe bn.ac DataBus[2];
Probe bn.ad DataBus[1];
Probe bn.ae DataBus[0];

Probe "I" da-ea.aa IR_ID[15];
Probe "D" da-ea.ab IR_ID[14];
Probe ":" da-ea.ac IR_ID[13];
Probe da-ea.ad IR_ID[12];
Probe "I" da-ea.ae IR_ID[11];
Probe "R" db-eb.aa IR_ID[10];
Probe db-eb.ab IR_ID[9];
Probe db-eb.ac IR_ID[8];
Probe db-eb.ad IR_ID[7];
Probe db-eb.ae IR_ID[6];
Probe dc-ec.aa IR_ID[5];
Probe dc-ec.ab IR_ID[4];
Probe dc-ec.ac IR_ID[3];
Probe dc-ec.ad IR_ID[2];
Probe dc-ec.ae IR_ID[1];
Probe dd-ed.aa IR_ID[0];

Probe "E" dd-ed.ad IR_EX[15];
Probe "X" dd-ed.ae IR_EX[14];
Probe ":" de-ee.aa IR_EX[13];
Probe de-ee.ab IR_EX[12];
Probe "I" de-ee.ac IR_EX[11];
Probe "R" de-ee.ad IR_EX[10];
Probe de-ee.ae IR_EX[9];
Probe df-ef.aa IR_EX[8];
Probe df-ef.ab IR_EX[7];
Probe df-ef.ac IR_EX[6];
Probe df-ef.ad IR_EX[5];
Probe df-ef.ae IR_EX[4];
Probe dg-eg.aa IR_EX[3];
Probe dg-eg.ab IR_EX[2];
Probe dg-eg.ac IR_EX[1];
Probe dg-eg.ad IR_EX[0];
Not dg-eg.ae ZERO _1;

Not dh-eh.aa ZERO _2;
Probe "M" dh-eh.ab IR_MEM[15];
Probe "E" dh-eh.ac IR_MEM[14];
Probe "M" dh-eh.ad IR_MEM[13];
Probe ":" dh-eh.ae IR_MEM[12];
Probe di-ei.aa IR_MEM[11];
Probe "I" di-ei.ab IR_MEM[10];
Probe "R" di-ei.ac IR_MEM[9];
Probe di-ei.ad IR_MEM[8];
Probe di-ei.ae IR_MEM[7];
Probe dj-ej.aa IR_MEM[6];
Probe dj-ej.ab IR_MEM[5];
Probe dj-ej.ac IR_MEM[4];
Probe dj-ej.ad IR_MEM[3];
Probe dj-ej.ae IR_MEM[2];
Probe dk-ek.aa IR_MEM[1];
Probe dk-ek.ab IR_MEM[0];

Probe "W" dk-ek.ae IR_WB[15];
Probe "B" dl-el.aa IR_WB[14];
Probe ":" dl-el.ab IR_WB[13];
Probe dl-el.ac IR_WB[12];
Probe "I" dl-el.ad IR_WB[11];
Probe "R" dl-el.ae IR_WB[10];
Probe dm-em.aa IR_WB[9];
Probe dm-em.ab IR_WB[8];
Probe dm-em.ac IR_WB[7];
Probe dm-em.ad IR_WB[6];
Probe dm-em.ae IR_WB[5];
Probe dn-en.aa IR_WB[4];
Probe dn-en.ab IR_WB[3];
Probe dn-en.ac IR_WB[2];
Probe dn-en.ad IR_WB[1];
Probe dn-en.ae IR_WB[0];

Probe "Stall_IF" ca stallIF;
Probe "Branch?" cb branchDecision;
Probe "Stall_ID" cd stallID;
Probe "Stall_EX" cg stallEX;
Probe "Stall_MEM" ck stallMEM;

Not ae.aa ZERO __3;
Probe "T" ae.ad Tag2[3];
Probe "a" ae.ae Tag2[2];
Probe "g" af.aa Tag2[1];
Probe "2" af.ab Tag2[0];
Probe "F" af.ae FR2[15];
Probe "R" ag.aa FR2[14];
Probe "2" ag.ab FR2[13];
Probe ag.ac FR2[12];
Probe ag.ad FR2[11];
Probe ag.ae FR2[10];
Probe ah.aa FR2[9];
Probe ah.ab FR2[8];
Probe ah.ac FR2[7];
Probe ah.ad FR2[5];
Probe ah.ae FR2[5];
Probe ai.aa FR2[4];
Probe ai.ab FR2[3];
Probe ai.ac FR2[2];
Probe ai.ad FR2[1];
Probe ai.ae FR2[0];

Not be.aa ZERO __2;
Probe "T" be.ad Tag1[3];
Probe "a" be.ae Tag1[2];
Probe "g" bf.aa Tag1[1];
Probe "1" bf.ab Tag1[0];
Probe "F" bf.ae FR1[15];
Probe "R" bg.aa FR1[14];
Probe "1" bg.ab FR1[13];
Probe bg.ac FR1[12];
Probe bg.ad FR1[11];
Probe bg.ae FR1[10];
Probe bh.aa FR1[9];
Probe bh.ab FR1[8];
Probe bh.ac FR1[7];
Probe bh.ad FR1[5];
Probe bh.ae FR1[5];
Probe bi.aa FR1[4];
Probe bi.ab FR1[3];
Probe bi.ac FR1[2];
Probe bi.ad FR1[1];
Probe bi.ae FR1[0];

Not ce.aa ZERO __0;
Probe "W" ce.ad WBD[3];
Probe "B" ce.ae WBD[2];
Probe "D" cf.aa WBD[1];
Probe cf.ab WBD[0];
Not cf.ae ZERO __1;

Probe "I" fa.aa PC1[15];
Probe "D" fa.ab PC1[14];
Probe ":" fa.ac PC1[13];
Probe fa.ad PC1[12];
Probe "P" fa.ae PC1[11];
Probe "C" fb.aa PC1[10];
Probe "1" fb.ab PC1[9];
Probe fb.ac PC1[8];
Probe fb.ad PC1[7];
Probe fb.ae PC1[6];
Probe fc.aa PC1[5];
Probe fc.ab PC1[4];
Probe fc.ac PC1[3];
Probe fc.ad PC1[2];
Probe fc.ae PC1[1];
Probe fd.aa PC1[0];
Not fd.ae ZERO _3;

Probe "I" ga.aa A[15];
Probe "D" ga.ab A[14];
Probe ":" ga.ac A[13];
Probe ga.ad A[12];
Probe "A" ga.ae A[11];
Probe gb.aa A[10];
Probe gb.ab A[9];
Probe gb.ac A[8];
Probe gb.ad A[7];
Probe gb.ae A[6];
Probe gc.aa A[5];
Probe gc.ab A[4];
Probe gc.ac A[3];
Probe gc.ad A[2];
Probe gc.ae A[1];
Probe gd.aa A[0];

Probe "I" ha.aa B[15];
Probe "D" ha.ab B[14];
Probe ":" ha.ac B[13];
Probe ha.ad B[12];
Probe "B" ha.ae B[11];
Probe hb.aa B[10];
Probe hb.ab B[9];
Probe hb.ac B[8];
Probe hb.ad B[7];
Probe hb.ae B[6];
Probe hc.aa B[5];
Probe hc.ab B[4];
Probe hc.ac B[3];
Probe hc.ad B[2];
Probe hc.ae B[1];
Probe hd.aa B[0];

Probe "I" ia.aa IR1[15];
Probe "D" ia.ab IR1[14];
Probe ":" ia.ac IR1[13];
Probe ia.ad IR1[12];
Probe "I" ia.ae IR1[11];
Probe "R" ib.aa IR1[10];
Probe "1" ib.ab IR1[9];
Probe ib.ac IR1[8];
Probe ib.ad IR1[7];
Probe ib.ae IR1[6];
Probe ic.aa IR1[5];
Probe ic.ab IR1[4];
Probe ic.ac IR1[3];
Probe ic.ad IR1[2];
Probe ic.ae IR1[1];
Probe id.aa IR1[0];
Not id.ae ZERO _4;

Probe "I" ja.aa D[15];
Probe "D" ja.ab D[14];
Probe ":" ja.ac D[13];
Probe ja.ad D[12];
Probe "D" ja.ae D[11];
Probe jb.aa D[10];
Probe jb.ab D[9];
Probe jb.ac D[8];
Probe jb.ad D[7];
Probe jb.ae D[6];
Probe jc.aa D[5];
Probe jc.ab D[4];
Probe jc.ac D[3];
Probe jc.ad D[2];
Probe jc.ae D[1];
Probe jd.aa D[0];

Probe "N" ff.aa-ab N;
Probe "Z" ff.ad-ae Z;

Probe "E" gd.ad ALUo[15];
Probe "X" gd.ae ALUo[14];
Probe ":" ge.aa ALUo[13];
Probe ge.ab ALUo[12];
Probe "A" ge.ac ALUo[11];
Probe "L" ge.ad ALUo[10];
Probe "U" ge.ae ALUo[9];
Probe "o" gf.aa ALUo[8];
Probe gf.ab ALUo[7];
Probe gf.ac ALUo[6];
Probe gf.ad ALUo[5];
Probe gf.ae ALUo[4];
Probe gg.aa ALUo[3];
Probe gg.ab ALUo[2];
Probe gg.ac ALUo[1];
Probe gg.ad ALUo[0];
Not gg.ae ZERO _5;

Probe "E" hd.ad DMAR[15];
Probe "X" hd.ae DMAR[14];
Probe ":" he.aa DMAR[13];
Probe he.ab DMAR[12];
Probe "D" he.ac DMAR[11];
Probe "M" he.ad DMAR[10];
Probe "A" he.ae DMAR[9];
Probe "R" hf.aa DMAR[8];
Probe hf.ab DMAR[7];
Probe hf.ac DMAR[6];
Probe hf.ad DMAR[5];
Probe hf.ae DMAR[4];
Probe hg.aa DMAR[3];
Probe hg.ab DMAR[2];
Probe hg.ac DMAR[1];
Probe hg.ad DMAR[0];
Not hg.ae ZERO _7;

Probe "E" jd.ad SMDR[15];
Probe "X" jd.ae SMDR[14];
Probe ":" je.aa SMDR[13];
Probe je.ab SMDR[12];
Probe "S" je.ac SMDR[11];
Probe "M" je.ad SMDR[10];
Probe "D" je.ae SMDR[9];
Probe "R" jf.aa SMDR[8];
Probe jf.ab SMDR[7];
Probe jf.ac SMDR[6];
Probe jf.ad SMDR[5];
Probe jf.ae SMDR[4];
Probe jg.aa SMDR[3];
Probe jg.ab SMDR[2];
Probe jg.ac SMDR[1];
Probe jg.ad SMDR[0];
Not jg.ae ZERO _8;

Not gh.aa ZERO _6;
Probe "M" gh.ab ALUo1[15];
Probe "E" gh.ac ALUo1[14];
Probe "M" gh.ad ALUo1[13];
Probe ":" gh.ae ALUo1[12];
Probe gi.aa ALUo1[11];
Probe "A" gi.ab ALUo1[10];
Probe "L" gi.ac ALUo1[9];
Probe "U" gi.ad ALUo1[8];
Probe "o" gi.ae ALUo1[7];
Probe "1" gj.aa ALUo1[6];
Probe gj.ab ALUo1[5];
Probe gj.ac ALUo1[4];
Probe gj.ad ALUo1[3];
Probe gj.ae ALUo1[2];
Probe gk.aa ALUo1[1];
Probe gk.ab ALUo1[0];

Not jh.aa ZERO _9;
Probe "M" jh.ab LMDR[15];
Probe "E" jh.ac LMDR[14];
Probe "M" jh.ad LMDR[13];
Probe ":" jh.ae LMDR[12];
Probe ji.aa LMDR[11];
Probe "L" ji.ab LMDR[10];
Probe "M" ji.ac LMDR[9];
Probe "D" ji.ad LMDR[8];
Probe "R" ji.ae LMDR[7];
Probe jj.aa LMDR[6];
Probe jj.ab LMDR[5];
Probe jj.ac LMDR[4];
Probe jj.ad LMDR[3];
Probe jj.ae LMDR[2];
Probe jk.aa LMDR[1];
Probe jk.ab LMDR[0];

Not fk.aa ZERO _10;
Probe "R" fk.ae Reg0[15];
Probe "e" fl.aa Reg0[14];
Probe "g" fl.ab Reg0[13];
Probe "0" fl.ac Reg0[12];
Probe fl.ad Reg0[11];
Probe fl.ae Reg0[10];
Probe fm.aa Reg0[9];
Probe fm.ab Reg0[8];
Probe fm.ac Reg0[7];
Probe fm.ad Reg0[6];
Probe fm.ae Reg0[5];
Probe fn.aa Reg0[4];
Probe fn.ab Reg0[3];
Probe fn.ac Reg0[2];
Probe fn.ad Reg0[1];
Probe fn.ae Reg0[0];

Probe "R" gk.ae Reg1[15];
Probe "e" gl.aa Reg1[14];
Probe "g" gl.ab Reg1[13];
Probe "1" gl.ac Reg1[12];
Probe gl.ad Reg1[11];
Probe gl.ae Reg1[10];
Probe gm.aa Reg1[9];
Probe gm.ab Reg1[8];
Probe gm.ac Reg1[7];
Probe gm.ad Reg1[6];
Probe gm.ae Reg1[5];
Probe gn.aa Reg1[4];
Probe gn.ab Reg1[3];
Probe gn.ac Reg1[2];
Probe gn.ad Reg1[1];
Probe gn.ae Reg1[0];

Not hk.aa ZERO _11;
Probe "R" hk.ae Reg2[15];
Probe "e" hl.aa Reg2[14];
Probe "g" hl.ab Reg2[13];
Probe "2" hl.ac Reg2[12];
Probe hl.ad Reg2[11];
Probe hl.ae Reg2[10];
Probe hm.aa Reg2[9];
Probe hm.ab Reg2[8];
Probe hm.ac Reg2[7];
Probe hm.ad Reg2[6];
Probe hm.ae Reg2[5];
Probe hn.aa Reg2[4];
Probe hn.ab Reg2[3];
Probe hn.ac Reg2[2];
Probe hn.ad Reg2[1];
Probe hn.ae Reg2[0];

Not ik.aa ZERO _12;
Probe "R" ik.ae Reg3[15];
Probe "e" il.aa Reg3[14];
Probe "g" il.ab Reg3[13];
Probe "3" il.ac Reg3[12];
Probe il.ad Reg3[11];
Probe il.ae Reg3[10];
Probe im.aa Reg3[9];
Probe im.ab Reg3[8];
Probe im.ac Reg3[7];
Probe im.ad Reg3[6];
Probe im.ae Reg3[5];
Probe in.aa Reg3[4];
Probe in.ab Reg3[3];
Probe in.ac Reg3[2];
Probe in.ad Reg3[1];
Probe in.ae Reg3[0];

Probe "R" jk.ae Reg4[15];
Probe "e" jl.aa Reg4[14];
Probe "g" jl.ab Reg4[13];
Probe "4" jl.ac Reg4[12];
Probe jl.ad Reg4[11];
Probe jl.ae Reg4[10];
Probe jm.aa Reg4[9];
Probe jm.ab Reg4[8];
Probe jm.ac Reg4[7];
Probe jm.ad Reg4[6];
Probe jm.ae Reg4[5];
Probe jn.aa Reg4[4];
Probe jn.ab Reg4[3];
Probe jn.ac Reg4[2];
Probe jn.ad Reg4[1];
Probe jn.ae Reg4[0];

Not kk.aa ZERO _13;
Probe "R" kk.ae Reg5[15];
Probe "e" kl.aa Reg5[14];
Probe "g" kl.ab Reg5[13];
Probe "5" kl.ac Reg5[12];
Probe kl.ad Reg5[11];
Probe kl.ae Reg5[10];
Probe km.aa Reg5[9];
Probe km.ab Reg5[8];
Probe km.ac Reg5[7];
Probe km.ad Reg5[6];
Probe km.ae Reg5[5];
Probe kn.aa Reg5[4];
Probe kn.ab Reg5[3];
Probe kn.ac Reg5[2];
Probe kn.ad Reg5[1];
Probe kn.ae Reg5[0];

Not lk.aa ZERO _14;
Probe "R" lk.ae Reg6[15];
Probe "e" ll.aa Reg6[14];
Probe "g" ll.ab Reg6[13];
Probe "6" ll.ac Reg6[12];
Probe ll.ad Reg6[11];
Probe ll.ae Reg6[10];
Probe lm.aa Reg6[9];
Probe lm.ab Reg6[8];
Probe lm.ac Reg6[7];
Probe lm.ad Reg6[6];
Probe lm.ae Reg6[5];
Probe ln.aa Reg6[4];
Probe ln.ab Reg6[3];
Probe ln.ac Reg6[2];
Probe ln.ad Reg6[1];
Probe ln.ae Reg6[0];

Not mk.aa ZERO _15;
Probe "R" mk.ae Reg7[15];
Probe "e" ml.aa Reg7[14];
Probe "g" ml.ab Reg7[13];
Probe "7" ml.ac Reg7[12];
Probe ml.ad Reg7[11];
Probe ml.ae Reg7[10];
Probe mm.aa Reg7[9];
Probe mm.ab Reg7[8];
Probe mm.ac Reg7[7];
Probe mm.ad Reg7[6];
Probe mm.ae Reg7[5];
Probe mn.aa Reg7[4];
Probe mn.ab Reg7[3];
Probe mn.ac Reg7[2];
Probe mn.ad Reg7[1];
Probe mn.ae Reg7[0];
