/* From cmcclun: file `/home/cmcclun/cs355/pj9/comm.h' as assignment pjX-4 */
/* Comm.h by Chris McCLung cs355 2001*/
/* THIS CODE IS MY OWN WORK, IT WAS WRITTEN WITHOUT CONSULTING A TUTOR OR CODE WRITTEN BY OTHER STUDENTS - Chris McCLung */ 


Define Comm Phase[1-4] RD WR MAR MBR MARData[15..0] DataBusIn[15-0] C[15..0]
       | MReq READ AddrBus[15..0] DataBusOut[15..0] MBROutput[15..0];
    
  /* Construct MREQ and READ signals */
	  
  Not aa Phase[1] np1; Not aa Phase[3] np3; Not aa Phase[4] np4; 
  And aa RD np1 rd;
  And aa WR np3 np4 wr;
  Xor aa RD WR MReq;
	  
  And aa RD READ;
      
  Write-Logic aa RD WR MBR Phase[4] | MBR-clk;
      
  Mux-mxn aa DataBusIn[15..0] C[15..0] RD | MBR-in[15..0] ;
/*
  Register cc MBR-in[15..0] MBR-clk | MBROutput[15..0];
*/
  ResetableReg16 cc MBR-in[15..0] MBR-clk ZERO | MBROutput[15..0];

  /* Here's the MAR-clk logic */
      
  And aa MAR Phase[3] nMAR-clk;
  Not aa nMAR-clk MAR-clk;

/*
  Register cc MARData[15..0] MAR-clk | AddrBus[15..0];
*/

  ResetableReg16 cc MARData[15..0] MAR-clk ZERO | AddrBus[15..0];
  /* Consider wiring not-WR to the enable switch */
      
      Not aa WR nwr;
  
      /* One way to get around read after write issues */
      Dff aa ONE nwr np1 ONE q q1;
	  Tri-Bus-16 aa MBROutput[15..0] q | DataBusOut[15..0];

Endef;


/* Defines the write logic of the comm component */
Define Write-Logic RD WR MBR-en Sys-clk | write;
Xor aa RD WR rw;
Nand aa rw MBR-en Sys-clk write;
Endef;

/* 16 Bit- tri-state buffer bus */
Define Tri-Bus-16 in[15..0] enable | out[15..0] ;

Tri-state-buffer aa in[15] enable | out[15];
Tri-state-buffer aa in[14] enable | out[14];
Tri-state-buffer aa in[13] enable | out[13];
Tri-state-buffer aa in[12] enable | out[12];
Tri-state-buffer aa in[11] enable | out[11];
Tri-state-buffer aa in[10] enable | out[10];
Tri-state-buffer aa in[9] enable | out[9];
Tri-state-buffer aa in[8] enable | out[8];
Tri-state-buffer aa in[7] enable | out[7];
Tri-state-buffer aa in[6] enable | out[6];
Tri-state-buffer aa in[5] enable | out[5];
Tri-state-buffer aa in[4] enable | out[4];
Tri-state-buffer aa in[3] enable | out[3];
Tri-state-buffer aa in[2] enable | out[2];
Tri-state-buffer aa in[1] enable | out[1];
Tri-state-buffer aa in[0] enable | out[0];

Endef;