/* From cmcclun: file `/home/cmcclun/cs355/pj9/mem.h' as assignment pjX-5 */
/* Memory Component */
/* Chris McCLung Spring 2001 */

Define Memory MReq Read Addr[15-0] DataIn[15-0] | DataOut[15..0];

And aa Read MReq activeRead;

/* 5.1 Address Circuit 1  enables reading from databus*/ 
Not aa Addr[6] N-a6;
Nand aa activeRead N-a6 addCirc-1;

Rom64x16  aa Addr[5-0] addCirc-1 ROMout[15..0] 
		  /* Program*/ 
		  10  4168  11  72   0 0 0 0 
		  0  0  15  65535    0 0 0 0  
		  0 0 0 0   0 0 0 0  0 0 0 0  0 0 0 0 
		  0 0 0 0   0 0 0 0  0 0 0 0  0 0 0 0 
		  0 0 0 0   0 0 0 0  0 0 0 0  0 0 0 0; 
Tri-Bus-16b aa ROMout[15..0] addCirc-1 |DataOutROM[15..0];

Addr2 aa MReq Read Addr[6] | rw enRam enTriRam;  
Ram64x8 aa DataIn[15..8] Addr[5..0] rw enRam ramOut[15..8]; 
Ram64x8 aa DataIn[7..0] Addr[5..0] rw enRam ramOut[7..0]; 
Tri-Bus-16b aa ramOut[15..0] enTriRam |DataOutRAM[15..0];
Mux-mxn aa DataOutRAM[15..0] DataOutROM[15..0] Addr[6] | DataOut[15..0];

Endef;

/* Outputs the ram-logic */
Define Addr2 MREQ Read A6 | RW En TriEn;

And aa Read ONE RW;
Nand aa MREQ A6 En;
Nand aa MREQ A6 Read TriEn;
Endef;

/* 16 Bit- tri-state buffer bus */
Define Tri-Bus-16b in[15..0] enable | out[15..0] ;

Tri-state-buffer aa in[15] enable | out[15];
Tri-state-buffer aa in[14] enable | out[14];
Tri-state-buffer aa in[13] enable | out[13];
Tri-state-buffer aa in[12] enable | out[12];
Tri-state-buffer aa in[11] enable | out[11];
Tri-state-buffer aa in[10] enable | out[10];
Tri-state-buffer aa in[9] enable | out[9];
Tri-state-buffer aa in[8] enable | out[8];
Tri-state-buffer aa in[7] enable | out[7];
Tri-state-buffer aa in[6] enable | out[6];
Tri-state-buffer aa in[5] enable | out[5];
Tri-state-buffer aa in[4] enable | out[4];
Tri-state-buffer aa in[3] enable | out[3];
Tri-state-buffer aa in[2] enable | out[2];
Tri-state-buffer aa in[1] enable | out[1];
Tri-state-buffer aa in[0] enable | out[0];

Endef;

/* Some little tests of the logic for RAM request/write
Switch aa a1 ZERO;
Switch ab a2 ZERO;
Switch ac a3 ZERO;

Addr2 bb a1 a2 a3 | b1 b2 b3;

Probe ca b1;
Probe cb b2;
Probe cc b3;
*/