CS355 Sylabus

Execution of a machine instruction under sequencing control

Sequencing - under direction of the 4 phase clock - will activate different parts of the datapath at different times.
The bits in the machine instructions sets up the swicthes in the datapath and make the data "flow" in different directionrs.
Let us consider the full picture and see:
1. how the datapath is setup by the bits in the machine instruction
2. and how the datapath - under direction of the 4 phase clock - move the data through the datapath under various settings

Machine instruction: R5 = R1 + R2

The IR in the following figure shows the machine instruction that performs "R5 = R1 + R2" and the figure shows the steps/events that will happen in the datapath when this machine instruction is executed:
You have to study the bits in the MIR very carefully. Each bit controls some part of the datapath.
Remember also that different parts of the CPU are activated (instructed to update itself) at different times - in the order given by the 4-phase clock. So looking in the above figure, and following the signals of the 4-phase clock, you will see the following happening (I have colored the different parts that are updated with 4 different colors to make things easier to follow):
- Phase 1: The "next" machine instruction is loaded into the IR and the IR sends out control signals immediately.
  The control signals that is important in phase 1 are the A and B fields, which select the registers 0001 (R1) and 0010 (R2)
  BTW: the reason why these signals are important in phase 1 is because the A- and B-buffers are updated in the next phase and the input input the A- and B-buffers are selected by the A and B fields.
- Phase 2: A- and B-buffers are updated and captures the values of R1 and R2 and keep these values for the remainder of the CPU cycle.
- Phase 3: phase 3 has 2 different uses in different machine instructions. The first use is to allow the ALU and Shifter time to do the computation - which is happening in this example.
  The second use of phase 3 is to update the MAR, this does not happen in this machine instruction. We will see one such instruction below.
- Phase 4: in phase 4, the result is written to the destination. The destination can be a register or the MBR (in the case of a memory write instruction). In this example, register R5 (0101 indicates register 5) will be updated because ENC bit = 1. On the other hand, the MBR is not updated because the MBR bit in the MIR is equal to 0.
- In summary: R1 and R2 are first copied into A- and B-buffers, the ALU is instructed to add, the shifter does no shift, the result on the C-bus is thus R1 + R2, and this result is written into register R5.
NOTE: you can use cs355-demo-dp2 to see this instruction in life action.

Write operation: MOV R1, (R2)

The MIR in the following figure shows the machine instruction that performs "MOV R1, (R2)" - move data in R1 to memory location whose address is given in R2. The figure shows the steps/events/things that will happen in the datapath when this machine instruction is executed:

Again, study the bits in the MIR very carefully first. I will now guide you through the execution.... The datapath is going to do the same things again as the previous example. However, because values of the different controlling bits are different, different things will happen !
- Phase 1: The "next" machine instruction is loaded into the IR and the IR sends out control signals immediately.
  The control signals that is important in phase 1 are the A and B fields, which select the registers 0001 (R1) and 0010 (R2)
- Phase 2: A- and B-buffers are updated and captures the values of R1 and R2 and keep these values for the remainder of the CPU cycle.
- Phase 3: during phase 3, the ALU and Shifter gets time to do the computation - in this example, the ALU will output the first input (= R1) and the Shifter will not shift, so that the result R1 is produced on the C-bus
  Simultaneously, the MAR is updated with the value of the B-buffer (= R2) because the MAR bit in the machine instruction is 1 and allow the phase 3 clock to trigger update to the MAR.
- Phase 4: in phase 4, the result on the C-bus (= R1) is written to the destination. The destination in this example is the MBR and not any register - you can tell this from the fact that the MBR bit of the machine instruction is 1 (update MBR) and the ENC bit is 0 (do not update any register).
- In summary: R1 is copied into MBR and R2 is copied into MAR.
Notes:
- Following the above machine instruction, the CPU will pause until the data in the MBR has been transfered to memory.
  The transference of data proceeds under a very rigid sequence of operation called "bus protocol". Bus protocols will be studied after we completed the discussion on the CPU architecture
- You can pause the CPU in different ways. The simplest way is stop the 4-phase clock.
  But sometimes it is necessary to run the CPU to "refresh" the data stored in various registers. In that case, a "dummy" machine instruction can be used to run the CPU that "does not do any harm". You can only do harm when you update values in registers.... So by blocking out all the update bits MAR, MBR and ENC in the machine instruction, the datapath will do the transfer and compute normally, but the result will not be used to update any register.
  The following is an example of a "dummy" machine instruction that make the datapath go through its normal operational cycle but does not update any registers:

Example Program: (Demo above code)

/home/cs355001/demo/datapath/cs355-demo-dp2.Wr Click the ' key to run Click the / key 4 times At the very end of the 3rd phase: observe mar[15..0] is updated with B At the very end of the 3rd phase: observe mbr[15..0] is updated with A
To simulate the 2nd step (write data in MBR to memory), change the machine instruction to: 1. Reset MBR=0, MAR=0 2. Reset EnC=0 3. Set MEM=1, R/W=0 (for write) Click key / 4 times ! (You don't see any effect, because the simulation does not include the memory component...)

Read operation: MOV (R2), R5

The MIR in the following figures shows the machine instruction that performs "MOV (R2), R5" - move data from memory location whose address is given in R2 into register R5.
The read operation is somewhat different from the write operation because the CPU needs to wait for the memory to return the data read in MBR before it can proceed to update the destination register (which is R5 in this example)....
The CPU must execute at least two machine instructions to read data from memory and store it in a register.
Also, depending on how fast the memory can return the data requested, the CPU may or may not need to wait even longer...

Let us consider what needs to be done under the ideal circumstance: when the memory is infinitely fast, i.e., as soon as the memory receives the read request with the proper address, the memory can return the data immediately.

The following is the first instruction that is executed by the CPU in a memory read operation:

I will now guide you through the execution.... The datapath is going to do the same things again as the previous example. However, because values of the different controlling bits are different, different things will happen !
- Remember that: to perform a memory read operation, the CPU needs to send out the address on the address bus and get the memory data into MBR...
- Phase 1: The "next" machine instruction is loaded into the MIR and the MIR sends out control signals immediately.
  The control signals that is important in phase 1 is the B field, which select the registers 0010 (R2) for the B-buffer (because this is how the address will be loaded into the MAR in phase 3).
  Notice that the destination register R5 is not written by this machine instruction ! The data must come into MBR first before it gets transfered into R5 !
- Phase 2: B-buffer (and A-buffer - but A-buffer value is not used) will are updated and capture the value of R2 and keep this values for the remainder of the CPU cycle.
- Phase 3: during phase 3, the ALU and Shifter gets time to do useless computation (yes, it is unavoidable to "waste" things in machines).
  Simultaneously, (and that is what is really important in the read opeartion) the MAR is updated with the value of the B-buffer (= R2) because the MAR bit in the machine instruction is 1 and allow the phase 3 clock to trigger update to the MAR.
- Phase 4: we have assume that the memory is infinitely fast, so the data from memory will be ready on the databus as soon as the address in MAR is ready - which happens in phase 3...
  So the data will be ready on the databus during phase 4 and we can update the MBR with the data on data bus.
  The destination in this machine instruction is the MBR, you can tell this from the fact that the MBR bit of the machine instruction is 1 (update MBR).
- In summary: R2 is copied into MAR and immediately the memory retrieves the value from the address given by R2. This value is copied into the MBR.
Note:
After getting the data from memory into the MBR, the CPU must execute the following machine instruction to transfer the data from MBR to its final destination register (= R5):

Example Program: (Demo above code)

/home/cs355001/demo/datapath/cs355-demo-dp2.Rd Click the ' key to run Click the / key 4 times At the very end of the 3rd phase: observe mar[15..0] is updated with B At the very end of the 4rd phase: observe mbr[15..0] is updated with 1100110011001100 (data from DataBus)
To move the data in MBR to some register, change the machine instruction to: 1. Set A-Mux = 1 2. Reset MBR, MAR, RD (and WR) 3. Set ALU = 10, SHF = 00 (already correctly set) 4. Set EnC 5. Set C = register number Click key / 4 times !

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