CS355 Sylabus

CPU Micro Architecture

We will now embark to an important milestone where we will learn how the CPU works, and I mean exactly how it works.
The type of CPU that we will be study is "micro-programmed" where the CPU executes a "micro-program" (or a very tiny program) to process a computer assembler instruction.
The non-micro-programmed CPU is even simpler and execute the computer assembler instruction directly.
The micro-programmed CPU has the advantage that the hardware can be extremely simple and yet the CPU can execute quite complex instructions by "breaking down" the complex instructions in a number of simple steps - these simple steps are encoded in a "micro-program".
The CPU is remarkably simple in construct, believe or not...
The heart of the CPU is the datapath.
The data path is the circuitry inside the CPU that connects
- the registers to ALU
- ALU back to registers.
That is because most operations performed by the CPU takes:
- Operands from registers (get them from registers into the ALU)
- Result of the operations are written by to a register
Datapaths comes in different sizes and shapes and complexity, but the operations is basically the same. Due to time limitations (it's very hard to build a Pentium class datapath in one semester time without sending half the students to psychiatrists...), we will build a extremely simple datapath...
We will study and construct a CPU with the following simple data path:
The CPU has 16 registers (which will be given in detail later) and each register has 16 bits.
The ALU and shifter also operates on 16 bit inputs and produces 16 bit outputs.
By now, you should be very familiar with the ALU and the Shifter, as you have created them yourself in Project 3.
There are some details left out of the figure that has been discussed before, primarily:
- Connection from registers outputs to the ALU input
  (As you should know, you can use (a large number of) multiplexors to make the connection between registers and ALU. A register can be selected and the selection is under the control of the SRC1 and SRC2 operand fields in the assembler instruction.)
- Connection from ALU outputs to the registers inputs
  (As you should know, you use (a large number of) decoder to select the register that you wish to update. The register is selected under the control of the DESTINATION operand field in the assembler instruction.)
Also, there are two special purpose register added into the datapath to simplify timing relationships. It is simplier to construct a correctly working CPU circuit if the operands are stored close to the input of the ALU. That's why we have insert the A-latch and B-latch, which
As I mentioned above, the datapath primarily connects the registers to the ALU and back. But if these were the only connections, the CPU would be quite useless, since we can't introduce any data from memory.
Thus, multiplexors and various control signals are embedded into the datapath to allow the CPU to move data between various important sources and destinations.
The CPU operates in cycles and in a single cycle, one ALU operation on one or two operands can be performed.
The operands are always fetched from registers within the CPU (but you must take the term "registers" more widely, they not only include the general purpose registers (such as D0, D1, etc in M68000), but also special purpose registers (such as Program Counter, Instruction Registers, Memory Address Register (MAR), Memory Buffer Register (MBR) and other scratch registers hidden away from the assembler programmer.)
The following figure shows the primary dataflow through the datapath when the CPU executes an instruction:

There are other "secondary" (less often used) paths available that enable the CPU to fetch operands from memory or write operands to memory.
I like to emphasize the fact that the operands are always fetched from registers within the CPU.... Your obvious question will be: what about if an instruction operates on some operand in memory ? Wouldn't this kind of operands come from memory ?
The answer is: yes, ofcourse, but only at first. The data is fetched from memory and stored inside the Memory Buffer Register (MBR). Only after the CPU has fecthed the data into the MBR, the CPU can then operate on the data. As you may notice in the figure above, the MBR is a special purpose register is tied into the datapath, so the operand is still fetched from a register within the CPU...
We will next look at the different "data transportation paths" within the simple datapath above.