CS355 Sylabus

Controlling the ordering of events/actions in the datapath

Recall that the purpose of the datapath is to execute the command encoded in a micro instruction.
The datapath is wired in such a way that the following steps must be done in exactly the sequence below for the datapath to operate correctly:
1. Fetch the proper operands into the A-latch/MBR and B-latch
2. Give the ALU some time to operate on the operands in A-latch/MBR and B-latch
3. Write the result into a register or into MBR (for further transfer to memory)
If this order is not followed, then the wrong result will be written to the final destination.
To pace the timing of the execution of each step, an N-phase clock is used.
Recall that a clock in the computer is a device that generate a train (serie) of pulses:

The main purpose of the clock is to pace various devices inside the computer. By "pacing", I mean: to make sure things happen in a certain order.
The simple datapath that we are constructing has 4 different phases:
- Get the next micro instruction to execute. After getting the micro instruction, the next 3 phases will actually execute the command encoded by micro instruction...
- Get the operands into A- and B-latches
- Give ALU and shifter time to compute
- Write the result to MBR or a register
To pace the execution performed by our simple datapath, we need a 4-phase clock
A 4-phase clock will have 4 different outputs and the waves outputted on each output looks like as follows:
Notice that at any moment, exactly one output of the 4 outputs of the 4-phase clock is equal to ONE and all others are ZERO.
Just imaging what would happen if you would the output signals of the 4-phase clock to trigger different D-flipflops that are found on the datapath.
As you know, when a D-flipflop is triggered by a clock signal, only then it will update its output to be equal to its input.
We can pace the executing of the datapath by connecting:
- Those parts of the datapath that need to be updated first to the phase 1 output of the 4-phase clock (so that these parts will do their work first).
- Those parts of the datapath that need to be updated next to the phase 2 output of the 4-phase clock (so that these parts will do their work next).
- And so on.
If we look carefully at what the timing relationships are in the simple datapath, we will conclude that:
- MIR must be loaded with a new micro instruction first, so the MIR register will be connected to phase 1.
- Operands must be fetched into the A- and B-latches next, so the A- and B-latches are connected to phase 2.
- After the A- and B-latches have been updated, we can (things can branch off):
  - Update MAR with the B-latch output
  - and/or let ALU & shifter do the computation (they don't need a clock signal...)
  So we can connect the MAR write signal to phase 3.
- When the ALU/shifter finishes, we can update the MBR or a register with the shifter output, so we can connect the MBR and the registers to phase 4.
We therefore get the following connections:

Example: sequencing the execution of a micro-instruction

Suppose the next micro-instruction that is offerred to the CPU is as follows:
(Recall: this is the instruction R1 = R0 + R6)

Let us follow the 4 phase clock and see which memory elements will be updated during each phase of the clock:

During phase 1 (only the components connected to phase 1 of the clock will receive a activation signal):

Result:

The Micro-Instruction Register is updated with the next micro-instruction:
(This is the micro-instruction that will be executed during phase 2, 3, 4 of the 4-phased clock !!!)

During phase 2 (only the components connected to phase 2 of the clock will receive a activation signal):

Result:

The A/B latches are updated with the values in the registers selected by 0000 (R0) and 0110 (R6):
(Recall: This micro-instruction is R1 = R0 + R6, the CPU has just fetched the input operands R0 and R6 !!!)

During phase 3 (only the components connected to phase 3 of the clock will receive a activation signal):

Result:

No memory elements are being updated during phase 3.
The purpose of Phase 3 is provide time to allow the computation to be performed
(Electricity takes some time to flow through the ALU, because it has many gate delays !!!)
The computation (R0+R6) will now arrive at the inputs of the registers:
(Recall: a register will not update its value until it receives a clock (write) signal)

During phase 4 (only the components connected to phase 4 of the clock will receive a activation signal):

Result:

One of the register (the one selected by the C value (0001) will receive a clock signal
This is the register R1
Therefore:
The register R1 will be updated with the value R0+R6 !!!

After phase 4, we will be back to phase 1:
And so on, and so on....

I have also wired the 4-phase clock in a demo program so you can experiment the result hands on. Just run:
How to operate:
- Switch off Reset first (press key ' (next to the ENTER key) once)
- Use switches in the top-right hand corner to setup the instruction that you want to execute
- After setting up a micro instruction do:
  - Toggle the key '/' 4 times up and down --- this will make the 4-phased clock go 1 complete cycle
- Observe carefully the order of execution:
  - (Phase 0) Set up the micro instruction
  - (Phase 1) Load operands into A- & B-latches
  - (Phase 2) Performs operation
  - (phase 3) Write back result.
  It's like "clock work"...
How a 4-phase clock is constructed in reality:
A crystal generates a clock-wave that is split off into 4 output. By placing "delays" between the cystal signal and the output, we can shift the wave in time. The "delays" are nothing more than a long piece of copper wire so that the electricity must travel a longer distance to different outputs:
The crystal element generates the following clock wave form: