Prologue

In 2010, the student Aaron Bush has built this pipelined CPU in his honor thesis project (he was a Chemistry (pre-med) and CS major double major and went to Univ. of Miami Med School after graduation)
Aaron also had to design an instruction format so that the pipeline CPU can execute them.
Understanding the instruction format will help you understand how the pipeline CPU operates

Encoding the instruction types

Each instruction is 2 bytes (= 16 bits)

The first 2 bits encodes the instruction type:

OpCode +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | x | x | | | | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ x x Instruction Type --------------------------------------------------------------- 0 0 ALU (2 registers or 1 register,1 constant operand) 0 1 Load (memory) 1 0 Store (memory) 1 1 Branch

Instruction Encoding format for (all) ALU instructions

Syntax: add destReg, srcReg1, srcReg2 sub destReg, srcReg1, srcReg2 add destReg, srcReg1, #const sub destReg, srcReg1, #const ... etc Endcoding: Dest Reg OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | D | D | D | P | 0 | | | | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not update PSR) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR Examples: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | P | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | sub r1,r2,r3 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | P | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | sub r1,r2,#3 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Where do you find source operands in ALU instructions

Syntax: add destReg, srcReg1, srcReg2 sub destReg, srcReg1, srcReg2 add destReg, srcReg1, #const sub destReg, srcReg1, #const ... etc Endcoding: Dest Reg OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | D | D | D | P | 0 | | | | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not update PSR) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR Examples: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | P | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | sub r1,r2,r3 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | P | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | sub r1,r2,#3 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Instruction Encoding format for the LDR (load) instructions

Syntax: LDR destReg, [srcReg1, constant] LDR destReg, [srcReg1, srcReg2] Encoding: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | D | D | D | x | 0 | 0 | 0 | x | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR Examples: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | ldr r6,[r3,r2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | ldr r6,[r3,#2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Where do you find source operands in LDR (load) instructions

Syntax: LDR destReg, [srcReg1, #const] LDR destReg, [srcReg1, srcReg2] Encoding: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | D | D | D | x | 0 | 0 | 0 | x | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR Examples: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | ldr r6,[r3,r2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | ldr r6,[r3,#2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Instruction Encoding format for the STR (store) instructions

Syntax: STR destReg, [srcReg1, #const] STR destReg, [srcReg1, srcReg2] Encoding: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | D | D | D | x | 0 | 0 | 0 | x | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR Examples: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | str r6,[r3,r2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | str r6,[r3,#2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Where do you find source operands in STR (store) instructions

Syntax: STR destReg, [srcReg1, #const] The destReg is used as a source reg in STR !! STR destReg, [srcReg1, srcReg2] (The destination of STR instr is memory !) Encoding: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | D | D | D | x | 0 | 0 | 0 | x | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR Examples: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | str r6,[r3,r2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | str r6,[r3,#2] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Instruction Encoding format for the Branch instructions

Syntax: BRA label BEQ label ... etc Encoding: Branch condition <------- relative branch offset -----------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | B | B | B | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ B B B Branch condition --------------------------------------------------------------- 0 0 0 Branch always 0 0 1 BEQ 0 1 0 BNE 0 1 1 BLT 1 0 0 BLE 1 0 1 BGT 1 1 0 BGE 1 1 1 not used Example: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ branch always to the address PC + 3

Where do you find source operands in Branch instructions

Syntax: BRA label and: the PC is always a source operand in branch !! BEQ label Encoding: Branch condition <------- relative branch offset -----------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | B | B | B | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ B B B Branch condition --------------------------------------------------------------- 0 0 0 Branch always 0 0 1 BEQ 0 1 0 BNE 0 1 1 BLT 1 0 0 BLE 1 0 1 BGT 1 1 0 BGE 1 1 1 not used Example: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | and the PC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ branch always to the address PC + 3