Review:
instruction encoding of the
str instruction
The STORE instruction encoding format (meaning of the bits in the instruction):
I will only discuss the register as 2nd source operand (the constant operand is similar)
How the pipeline CPU executes
str r1, [r2,r3]
Clock cycle 1: The IF stage fetches the instruction into the IR(ID) register
I have include the instruction code in binary
How the pipeline CPU executes
str r1, [r2,r3]
Start of clock cycle 2: the ID stage fetch all possible source operands
Notice the str instruction uses 3 source operands !!!
How the pipeline CPU executes
str r1, [r2,r3]
End of clock cycle 2: all source operands are fetched - now R1, R2 and R3 will be used
Notice: the instruction is moved into the IR(EX) register
How the pipeline CPU executes
str r1, [r2,r3]
Start of clock cycle 3: the EX stage operates on the correct source operands
The EX stage computes the memory address R2+R3 used by str r1,[r2,r3] !!!
How the pipeline CPU executes
str r1, [r2,r3]
End of clock cycle 3: the result is stored in ALU Output and the Data Mem Addr registers
Notice: the instruction is moved into the IR(MEM) register
How the pipeline CPU executes
str r1, [r2,r3]
Start of clock cycle 4: the MEM stage executes the str r1, [r2,r3]
The MEM stage sends a WRITE request, address = R2+R3 and data = R1 WAIT !!!
How the pipeline CPU executes
str r1, [r2,r3]
Start of clock cycle 4: notice that the IF stage also wants to use the system bus
The MEM stage has priority over the IF stage !!! The IF stage must be stopped (paused) !
How the pipeline CPU executes
str r1, [r2,r3]
Solution: when MEM stage detects a str instruction, it sends a STALL signal to the IF stage
The STALL signal will (1) disable the clock signal in the IF stage (2) send a NOP instr to IR(ID)
How the pipeline CPU executes
str r1, [r2,r3]
The MEM stage executes the str instruction and sends a WRITE request on the system bus:
In response, the memory will store the data R1 in the memory address R2+R3
How the pipeline CPU executes
str r1, [r2,r3]
End of clock cycle 4: the str instruction has now completed its execution !!
Notice: a harmless NOP (no-op or "do nothing") instruction is inserted into the IR(ID) register
How the pipeline CPU executes
str r1, [r2,r3]
Start of clock cycle 5: the str instruction will not cause the WB stage perform any operation...
We can filter the clock signal to the registers with an AND gate using the str instr code (10)
How the pipeline CPU executes
str r1, [r2,r3]
End of clock cycle 5: no changes in registers...
Notice: the instruction has been into the discarded !! (no longer needed !!!)
NO DEMO
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