The BRANCH instruction(s) encoding format (meaning of the bits in the instruction:

I used bra label to denote bal label (or b label) because my old notes used this notation.

Clock cycle 1: The IF stage fetches the instruction into the IR(ID) register

I have include the instruction code in binary

Start of clock cycle 2: the ID stage fetch all possible source operands

Notice that the branch instruction will use the current value in the PC register !!

End of clock cycle 2: all source operands are fetched - but only PC and IR1=32 will be used

The label label is 32 bytes below the current instruction - that's why offset = 32

Start of clock cycle 3: the EX stage operates on the correct source operands

The branch instructions will always select PC and IR1 for source operands

End of clock cycle 3: the branch destination address (PC+32) is stored in ALU Output reg

Notice: 2 instructions following bra label have now been fetched !!!

Start of clock cycle 4: the MEM stage is used to execute the bra label instruction:

The MEM stage sends the select signal to MUX in the IF stage to update PC to the branch address (PC+32)

End of clock cycle 4: the PC is updated to the branch destination address (PC+32)

This branch destination address in assembler code would be marked by the label label

Start of clock cycle 5: WB stage is idle - The IF stage fetches instruction at address label

End of clock cycle 5: the instruction at the branch address is fetched

Notice: the (branch) instruction has been into the discarded !! (no longer needed !!!)