Review:
data forwarding circuitry that solved the
ALU instruction
read-after-write data hazard
We saw that this data forwarding circuitry can solve the read-after-write data hazard caused by an ALU instruction:
The second kind of
read-after-write data hazard
Recall there are 3 kinds of instructions
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There is a second kind of read-after-write data hazard:
ldr r1, [r2,r3] // Read data from memory address R2+R3 add r4, r1, r4 add r5, r1, r5 add r6, r1, r6 add r7, r1, r7 |
The ldr instruction writes (updates) the register R1
Immediately following the ldr instruction, another instruction(s) uses (= reads) the new value
The second kind
of read-after-write data hazard -
Example
Consider the following program fragment:
ldr r1, [r2+r3] // R1=240, R2=4, R3=24, R4=1, R5=2, R6=3, R7=4
// Value in R1 = 240 = 00001111 00000000
// R2+R3 = 4+24 = 28
// Suppose Memory[28] = 11111111 00000000
add r4, r1, r4 // Correct R4 = 11111111 00000001
add r5, r1, r5 // Correct R5 = 11111111 00000010
add r6, r1, r6 // Correct R4 = 11111111 00000011
add r7, r1, r7 // Correct R4 = 11111111 00000100
...
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We will examine the execution of this program fragment using the improved (with forwarding hardware) pipeline CPU
We use a concrete example execution to highlight (= determine) the problems (= errors) in the execution of this sequence of instructions
Review important fact:
the latest time
to obtain operands for an
instruction
The first moment that the pipelined CPU uses operands of an instruction is in the EX stage:
Therefore: the correct operands must be available when an instruction is inside the EX stage !!!
Read-after-write data hazard caused by
a ldr instruction
Initial state: Clock cycle 1 - instruction ldr r1,[r2,r3] fetched in IR(ID)
Read-after-write data hazard caused by
a ldr instruction
Start 2: ID stage fetch operands R2, R3, IF stage fetch add r4,r1,r4,
Read-after-write data hazard caused by
a ldr instruction
End 2: R2,R3 fetched, add r4,r1,r4 fetched
Read-after-write data hazard caused by
a ldr instruction
Start 3: EX stage computes R2+R3, ID stage fetch R1, R4, IF stage fetch add r5,r1,r5,
Notice: the new value of R1 must be read from memory (is not computed like add r1,r2,r3) !!
Read-after-write data hazard caused by
a ldr instruction
End 3: Address R2+R3 computed, R1,R4 fetched, add r5,r1,r5 fetched
Note: the R1 value in incorrect and the new value is not yet read from memory !!!
Read-after-write data hazard caused by
a ldr instruction
Start 4: LD: fetch new R1, EX: computes R1+R4, ID: fetch R1, R5, IF: stalls
Note: we cannot forward the new R1 value because it has not been fetched yet !!
Read-after-write data hazard caused by
a ldr instruction
End 4: new R1 value is fetched (in LMDR) - but add r4,r1,r4 used the old R1 value !!
Conclussion: data forwarding solution could not solve this data hazard...