Understand the branch delay:
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What do you need to execute a (any) instruction (in general):
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What do you need to execute a (conditional/unconditional) branch instruction:
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This diagram shows the information needed to execute a (conditional) branch instruction:
We must figure out
how soon
all the information
are available.
The answer to
this question will
determine
when a
(cond) branch instruction
can be executed...
It is obvious that the PC and the offset is available in the ID stage:
(1) Can we
obtain the
N,Z,V,C flag values of the
compare instruction ???
(2) We must be
able to
add
PC + offset !!!
The earliest pipeline stage that can execute a (any) branch instruction is the ID stage:
(1) We need an
extra
adder circuit to
perform PC + offset
(2) The
PSR must be
updated
in the
middle of
the clock period
to
obtain the
N,Z,V,C flag values!