---

How to program using a delayed branching instruction

---

• Review
  • Delayed branching:

    Due to the pipelined execution of instructions, the pipelined CPU design results in a delayed branching behavior: The branch instruction will fetch the next instruction (= the instruction that follows the branch instruction) before updating the Program Counter to the branch destination address

    ---

  • This behavior is problematic for assembler programmers who are used to branch instruction that do not have branch delay:

    S1 S2 bra L // Branch without delay S3 // S3 is NOT executed S4 ... L: S10 S11

    Assembler programs written under the no delay branch assumption will not execute correctly when the branch instruction has a delay effect !!!

  ---

  ---

  ---

  ---

• A simple way to remedy the problem
  • Assembler programmers can use the following simple rule to write their programs using a delayed branching instruction:

    After every branching instruction, such as: bra, bne, beq, bgt, .... bsr !!! rts !!! you must insert a nop (= no operation - this instruction does not do anything, it just waste time...)

    ---

    ---

  • Example:

    If a "traditional" assembler program look like this: S1 S2 bra L // Branch without delay S3 // S3 is NOT executed S4 ... L: S10 S11 then the assembler program using a delayed branching instruction can be written like this: S1 S2 bra L // Branch with 1 slot delay nop // nop will be executed (harmlessly) S3 // S3 is NOT executed S4 ... L: S10 S11

  ---

  ---

  ---

  ---

• Unsatisfactory solution
  • Problem with inserting a nop instruction:

    A nop instruction - although harmless - is useless It slows down the CPU execution !!!

  ---

  ---

  ---

  ---

• Prelude to understanding how to "remove" NOP instructions
  • Facts that you need to know when comparing 2 program executions:

    2 programs are equivalent if they execute the same sequence of instructions We can ignore any nop instructions when we compare instructions executed by different programs because: nop instruction does nothing.... We can also ignore any branching instructions when we compare instructions executed by different programs because: A branching instruction does not update any data registers !!! So it has no effect on the behavior of the program In fact, a branch instruction changes the sequence of instructions executed: By listing the sequence of instruction executed, we have basically nullified the effect of the branch instruction !!! We can ignore any cmp (compare) instructions because: They do not update any data registers (They are only used to affect the branch direction)

  ---

  ---

  ---

  ---

• Removing the NOP instruction after an UNCONDITIONAL branch instruction
  • Behavior of an unconditional branch instruction:

    Program with an unconditional branch: s1 s2 s3 bra Label nop s4 s5 .... Label: t1 t2 .... The sequence of instructions executed is: s1 s2 s3 bra Label nop t1 t2

    ---

    ---

  • Observation:

    The unconditional branch instruction does not need to test flags s3 is always executed

    ---

    ---

  • How to remove the dummy NOP instruction after an unconditional branch:

    Replace the nop instruction (in the "delay slot (location)" of the bra instruction) by: the instruction prior to the bra instruction

    ---

  • Example:

    Program with a nop instruction: s1 s2 s3 <----- Instruction prior to the BRA instr bra Label nop s4 s5 .... Label: t1 t2 .... Equivalent program, now without the nop instruction: s1 s2 bra Label s3 s4 s5 .... Label: t1 t2 ....

    ---

    ---

  • Reason why the 2 programs are equivalent:

    Original program: s1 s2 s3 <----- Instruction prior to the BRA instr bra Label nop s4 s5 .... Label: t1 t2 .... The sequence of instructions executed by the original program: s1 s2 s3 BRA nop t1 t2 ... Modified program: s1 s2 bra Label s3 s4 s5 .... Label: t1 t2 .... The sequence of instructions executed by the modified program: s1 s2 BRA S3 t1 t2 ... If we ignore the bra and the nop instructions, both program executes the same sequence of instructions: s1 s2 s3 t1 t2 ..... and therefore they are equivalent !!!!

    ---

  • Example Program: (Demo above code)                                                
    • Before removing NOP: click here
    • After removing NOP: click here

    How to run the program:

    Right click on link and save in a scratch directory To compile:   as255s sparc-bra-nop-1 To run:          /home/cs355000/bin/sparc Load program in EGTAPI and single step.

  ---

  ---

  ---

  ---

• Studying the behavior of a CONDITIONAL branch instruction
  • Behavior of an conditional branch instruction:

    Program with a conditional branch: s1 s2 s3 cmp ... bcc Label nop s4 s5 .... Label: t1 t2 .... Executed instructions when branch taken: s1 s2 s3 cmp ... bcc Label nop t1 t2 Executed instructions when branch not taken: s1 s2 s3 cmp ... bcc Label nop s4 s5 Observation: The conditional branch instruction needs to test the flags We cannot move the CMP ... instruction after the conditional branch

  ---

  ---

  ---

  ---

  ---

  ---

• Removing the NOP instruction after an CONDITIONAL branch instruction
  • Consider a program segment with a condition branch instruction:

    s1 s2 s3 cmp ... bcc Label // Conditional branch nop // NOP instruction in "delay slot" s4 s5 Label: t1 t2 ....

    ---

  • There are 2 possible sequences of instruction executions:

    Seq. when branch is taken: s1 s2 s3 cmp bcc nop t1 t2 .... Seq. when branch not taken: s1 s2 s3 cmp bcc nop s4 s5 t1 t2 ....

    ---

    ---

  • Initial attempt for an nop replacement allgorithm:

    1. Replace the nop instruction by Copying the target instruction of the branch (= t1) 2. Move the target instruction of the branch (= t1) above the branch label

    Example:

    Original program: s1 s2 s3 cmp ... bcc Label // Conditional branch nop // NOP instruction in "delay slot" s4 s5 Label: t1 t2 .... Replace the nop instruction by copy the target instruction of the branch: s1 s2 s3 cmp ... bcc Label // Conditional branch t1 // Copied target instruction and replaced nop s4 s5 Label: t1 t2 .... Move the target instruction of the branch (= t1) above the branch label: s1 s2 s3 cmp ... bcc Label // Conditional branch t1 // Copied target instruction and replaced nop s4 s5 t1 Label: t2 ....

    ---

    ---

  • Let's compare the execution of the 2 programs:

    Original program: s1 s2 s3 cmp ... bcc Label // Conditional branch nop // NOP instruction in "delay slot" s4 s5 Label: t1 t2 .... The 2 possible sequences of instruction executions: Seq. when branch is taken: s1 s2 s3 cmp bcc nop t1 t2 .... Seq. when branch not taken: s1 s2 s3 cmp bcc nop s4 s5 t1 t2 .... Modified program: s1 s2 s3 cmp ... bcc Label // Conditional branch t1 // Copied target instruction and replaced nop s4 s5 t1 Label: t2 .... The 2 possible sequences of instruction executions: Seq. when branch is taken: s1 s2 s3 cmp bcc t1 t2 .... Seq. when branch not taken: s1 s2 s3 cmp bcc t1 s4 s5 t1 t2 ....

    ---

  • Conclusion:

    When the branch is taken, the 2 programs as equivalent When the branch is not taken, the modified program will have: executed the instruction t1 (= the instruction in the delay slot of the branch instruction) extraneously !!!

    ---

    ---

  • Fact:

    We cannot make the 2 programs equivalent without some modifications to the pipelined CPU !!!

  ---

  ---

  ---

  ---

  ---

  ---

• Annulling branch instruction
  • The pipelined CPU has an annulling version of each branch instruction

  • Effect of am annulling branch:

    When the branch instruction takes the branch, the instruction in the delay slot will be executed When the branch instruction fails to branch, the instruction in the delay slot is annulled (voided) !!! Technical note: The instruction in the delay slot is actually replaced by a NOP instruction

    ---

  • Circuitry used to implement the annulling branch:

    Explanation:

    When the branch is taken, the select signal (the magenta lines in the figure) will select: The branch address for the PC The instruction from the data bus for the ID stage. When the branch is not taken, the select signal (the magenta lines in the figure) will select: The value PC + 4 for the PC The NOP instruction for the ID stage (thus voiding the instruction fetched from the data bus !!!)

    ---

    ---

  • Notation for an annulling branch instruction:

    bcc,a Label E.g.: blt,a label

  ---

  ---

  ---

  ---

• Removing the NOP instruction after a conditional branch: the full scope
  • Algorithm for removing a nop instruction after a conditional branch :

    1. Replace the nop instruction by Copying the target instruction of the branch (= t1) 2. Move the target instruction of the branch (= t1) above the branch label 3. Replace the branch by its annulling version

    ---

    Example:

    Original program: s1 s2 s3 cmp ... bcc Label // Conditional branch nop // NOP instruction in "delay slot" s4 s5 Label: t1 t2 .... Replace the nop instruction by copy the target instruction of the branch: s1 s2 s3 cmp ... bcc Label // Conditional branch t1 // Copied target instruction and replaced nop s4 s5 Label: t1 t2 .... Move the target instruction of the branch (= t1) above the branch label: s1 s2 s3 cmp ... bcc Label // Conditional branch t1 // Copied target instruction and replaced nop s4 s5 t1 Label: t2 .... Change the branch to its annulling version: s1 s2 s3 cmp ... bcc,a Label // The ANNULLING version of the Conditional branch t1 // Copied target instruction and replaced nop s4 s5 t1 Label: t2 ....

    ---

    ---

  • Let's compare the execution of the 2 programs:

    Original program: s1 s2 s3 cmp ... bcc Label // Conditional branch nop // NOP instruction in "delay slot" s4 s5 Label: t1 t2 .... The 2 possible sequences of instruction executions: Seq. when branch is taken: s1 s2 s3 cmp bcc nop t1 t2 .... Seq. when branch not taken: s1 s2 s3 cmp bcc nop s4 s5 t1 t2 .... Modified program: s1 s2 s3 cmp ... bcc Label // Conditional branch t1 // Copied target instruction and replaced nop s4 s5 t1 Label: t2 .... The 2 possible sequences of instruction executions: Seq. when branch is taken: s1 s2 s3 cmp bcc t1 t2 .... Seq. when branch not taken: s1 s2 s3 cmp bcc t1 s4 s5 t1 t2 ....

    ---

  • Conclusion:

    The 2 programs are equivalent !!!!

  ---

• Example Program: (Demo above code)                                                
  • Before removing NOP: click here
  • After removing NOP: click here

  How to run the program:

  Right click on link and save in a scratch directory To compile:   as255s sparc-bra-nop-2 To run:          /home/cs355000/bin/sparc Load program in EGTAPI and single step.