~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~	Pipelines
~		These are the pipeline files with empty ROM (contains no instructions)
~		Addresses 0-63 are ROM
~		Addresses 64-127 are RAM
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

(1) BasicPipe
	This is a working implementation of the basic pipelined CPU
	Contains many data hazards
	Branch delay of 3 instructions

(2) AdvancedPipe
	This is a working implementation of the advanced pipelined CPU
	Fixes the read after write data hazard for ALU instructions
	- Uses 2 tag registers and 2 forwarding registers
	Fixes the read after write data hazard for LD instructions
	- Uses stalling and forwarding
	Fixes ST after write data hazards
	Reduces branch delay to 1 instruction

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~	Sample Programs
~		All programs start by initializing values into R1-R7
~		The initialization instructions are followed by 4 NOP instructions
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

(3) basic-demo
	Uses BasicPipe with a non-hazardous program
		R1 = R2 + R3
		R1 = R4 + R5
		R1 = R6 + R7

(4) alu-hazard
	Uses BasicPipe with a program that contains the ALU hazard
		R1 = R2 + R3
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1

(5) alu-fixed
	Uses AdvancedPipe to demonstrate fixing the ALU hazard
		R1 = R2 + R3
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1

(6) ld-hazard
	Uses BasicPipe with a program that contains the LD hazard
	Sets RAM address 66 to the value 4000
		R1 = mem(R2 + R3)
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1

(7) ld-fixed
	Uses AdvancedPipe to demonstrate fixing the LD hazard
	Sets RAM address 66 to the value 4000
		R1 = mem(R2 + R3)
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1

(8) bra-delay
	Uses BasicPipe to demonstrate the branch delay of 3 instructions
	- Unconditional branching
		goto LABEL
		R2 += R1
		R3 += R1
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1
		LABEL:

(9) bra-reduced
	Uses AdvancedPipe to demonstrate reducing the branch delay to 1 instruction
	- Unconditional branching
		goto LABEL
		R2 += R1
		R3 += R1
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1
		LABEL:

(10) brcond-delay
	Uses BasicPipe to demonstrate the branch delay of 3 instructions
	- Conditional branching
		if (R3 < r2) goto LABEL
		R2 += R1
		R3 += R1
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1
		LABEL:

(11) brcond-reduced
	Uses AdvancedPipe to demonstrate reducing the branch delay to 1 instruction
	- Conditional branching
		if (R3 < r2) goto LABEL
		R2 += R1
		R3 += R1
		R4 += R1
		R5 += R1
		R6 += R1
		R7 += R1
		LABEL:
