
Define Computer Tick Reset | 
  Phase[1-4]

  R0[15..0] R1[15..0] R2[15..0] R3[15..0] R4[15..0] R5[15..0]
  R6[15..0] R7[15..0] R8[15..0] R9[15..0] R10[15..0] R11[15..0]
  R12[15..0] R13[15..0] R14[15..0] R15[15..0]
  ABus[15-0] BBus[15-0] ALatch[15-0] BLatch[16-0]
  AMUX[15-0] ALUOut[15-0] C[15-0] N Z
  branch mir[31-0] MPC[7-0]
  MReq READ AddrBus[15..0] CommOut[15..0] mbr[15..0]
  DataBus[15..0];

  /* Here's the clock */
  Four-Phase-Clock qq Reset Tick | Phase[1-4];

  /* Datapath Component */

  DataPath rs mir[31..0] mbr[15-0] Phase [1-4] Reset |
      R0[15..0] R1[15..0] R2[15..0] R3[15..0] R4[15..0] R5[15..0]
      R6[15..0] R7[15..0] R8[15..0] R9[15..0] R10[15..0] R11[15..0]
      R12[15..0] R13[15..0] R14[15..0] R15[15..0]
      ABus[15-0] BBus[15-0] ALatch[15-0] BLatch[16-0]
      AMUX[15-0] ALUOut[15-0] C[15-0] N Z;

  /* MIR Component */

  MIR-Comp rt Reset N Z Phase[1-4] | branch mir[31-0] MPC[7-0];

  /* Communication Component */
  /* Wire mir signals to Rd and Write MAR and MBR... */ 
  /* Create Aliases For Convenience */
  And tt mir[24] ONE MBR;
  And tt mir[23] ONE MAR;
  And tt mir[22] ONE RD;
  And tt mir[21] ONE WR;

  Comm ss Phase[1-4] RD WR MAR MBR BBus[15..0] DataBus[15-0] C[15 ..0] 
          | MReq READ AddrBus[15..0] CommOut[15..0] mbr[15..0];


  /* attatch AddrBus and Databus out to memory component */ 

  Memory st MReq READ AddrBus[15..0] CommOut[15..0] | DataBus[15..0] ;

  Byte-probe-h "Mem" ud-ui DataBus[15..8];
  Byte-probe-h "DataBus" uj-uo DataBus[7..0];
Endef;

