/* From cmcclun: file `/home/cmcclun/cs355/pj9/clock.h' as assignment pjX-1 */
/* Clock by Chris McCLung */
/* 1 bit d-latch memory helper macro; adapted from Cheung */

Define One_bit_mem Data Clk | mem;
And 5d Data Clk set;  Nor 5e set mem q0-2;   
Not 6c Data Not-Data; And 6d Clk Not-Data reset; Nor 6e q0-2 reset mem; 
Endef;


/* Four-phase Clock Macro */
/* Returns to phase one when Reset = 1; Otherwise, it cycles from phase1 to phase
   4 with each tick */

Define Four-Phase-Clock Reset Tick | Phase[1..4];

Not aa Reset nr;

Or bg Reset q0-bar or1;
Dff bh nr or1 Tick ONE q0 q0-bar;

Xor bg q0 q1 xor1;
Or cg xor1 Reset or2;
Dff dh nr or2 Tick ONE q1 q1-bar;

And ha q0 q1 Phase[1];
And hb q0-bar q1-bar Phase[2];
And hc q0 q1-bar Phase[3];
And hd q0-bar q1 Phase[4];
Endef;

/*MPC-With-Reset Macro 
  Initializes MPC[7..0] to UNKNOWN 
  MPC[7..0] = 0, when reset equals one
  Otherwise MPC increments as an 8-bit number with each new tick
*/

Define MPC-With-Reset Reset Tick | MPC[7..0];

Not aa Reset nr;

/* Increment Circuit */

Full_Adder aa MPC[0] ONE ZERO | c1 Mh[0];
Full_Adder aa MPC[1] c1  ZERO | c2 Mh[1];
Full_Adder aa MPC[2] c2  ZERO | c3 Mh[2];
Full_Adder aa MPC[3] c3  ZERO | c4 Mh[3];
Full_Adder aa MPC[4] c4  ZERO | c5 Mh[4];
Full_Adder aa MPC[5] c5  ZERO | c6 Mh[5];
Full_Adder aa MPC[6] c6  ZERO | c7 Mh[6];
Full_Adder aa MPC[7] c7  ZERO | c8 Mh[7];

Dff aa ONE Mh[0] Tick nr newM0 x1;
Dff aa ONE Mh[1] Tick nr newM1 x2;
Dff aa ONE Mh[2] Tick nr newM2 x3;
Dff aa ONE Mh[3] Tick nr newM3 x4;
Dff aa ONE Mh[4] Tick nr newM4 x5;
Dff aa ONE Mh[5] Tick nr newM5 x6;
Dff aa ONE Mh[6] Tick nr newM6 x7;
Dff aa ONE Mh[7] Tick nr newM7 x8;

Or aa Reset Tick or-tick;

One_bit_mem aa newM0 or-tick | MPC[0];
One_bit_mem aa newM1 or-tick | MPC[1];
One_bit_mem aa newM2 or-tick | MPC[2];
One_bit_mem aa newM3 or-tick | MPC[3];
One_bit_mem aa newM4 or-tick | MPC[4];
One_bit_mem aa newM5 or-tick | MPC[5];
One_bit_mem aa newM6 or-tick | MPC[6];
One_bit_mem aa newM7 or-tick | MPC[7];

Endef;
