/* add1:

   input i1 i0
   output o2 o1 o0
   Effect: (o2 o1 o0) = (i1 i0) + 1
*/

Switch ca sw0 ZERO;
Switch ba sw1 ZERO;
 
Not cb sw1 not_sw1;
Not bb sw0 not_sw0;

/*------------------------- stage 1 ---------------------- */
And ac sw0     sw1       and_1;

And bc not_sw1 sw0       and_2a;
And bc sw1     not_sw0   and_2b;

And cc sw1     not_sw0   and_3a;
And cc not_sw1 not_sw0   and_3b;

/*------------------------- stage 2 ---------------------- */

Or bd and_2a   and_2b    o1;
Or cd and_3a   and_3b    o0;

/*------------------------- Probes ---------------------- */
 
Probe "o2" ae and_1;
Probe "o1" be o1;
Probe "o0" ce o0;

