/* 2-bit adder */

#include "Sim.h"

void simnet()
{
   /* ==============================================
      Use named signals for input and outputs
      ============================================== */
   Sig(a0,1); Sig(a1,1); Sig(b0,1); Sig(b1,1);       // The 2 bit numbers
   Sig(Carry,1); Sig(s1,1); Sig(s0,1);               // Output signals

   /* =====================================================
      Use unnamed signals for the intermediate results...
      ===================================================== */
   Signal na0, na1, nb0, nb1;            // Inverse of the inputs
   Signal c1, c2, c3, c4, c5, c6;
   Signal s01, s02, s03, s04, s05, s06, s07, s08;
   Signal s11, s12, s13, s14, s15, s16, s17, s18;

   /* ============================================
      Put up the switches
      ============================================ */
   Switch("ba",a0,'0',Zero); 
   Switch("aa",a1,'1',Zero); 
   Switch("da",b1,'2',Zero); 
   Switch("ea",b0,'3',Zero); 

   /* ============================================
      Make the complement signals
      ============================================ */
   Not("bb",a0,na0);
   Not("ab",a1,na1);
   Not("db",b1,nb1);
   Not("eb",b0,nb0);

   /* ============================================
      Probe the outputs
      ============================================ */
   Probe("be",Carry);
   Probe("ce",s1);
   Probe("de",s0);
   
   /* ===============================================================
      How to make a circuit quickly:

      I first write this line:

              And("bb", (b1,b0,a1,a0), cX);

      Then I cut and paste this line and make changes to the line
      =============================================================== */
   And("bc", (nb1,b0,a1,a0), c1);
   And("bc", (b1,nb0,a1,na0), c2);
   And("bc", (b1,nb0,a1,a0), c3);
   And("bc", (b1,b0,na1,a0), c4);
   And("bc", (b1,b0,a1,na0), c5);
   And("bc", (b1,b0,a1,a0), c6);
   
   And("cc", (nb1,nb0,a1,na0), s11);
   And("cc", (nb1,nb0,a1,a0), s12);
   And("cc", (nb1,b0,na1,a0), s13);
   And("cc", (nb1,b0,a1,na0), s14);
   And("cc", (b1,nb0,na1,na0), s15);
   And("cc", (b1,nb0,na1,a0), s16);
   And("cc", (b1,b0,na1,na0), s17);
   And("cc", (b1,b0,a1,a0), s18);
   
   And("dc", (nb1,nb0,na1,a0), s01);
   And("dc", (nb1,nb0,a1,a0), s02);
   And("dc", (nb1,b0,na1,na0), s03);
   And("dc", (nb1,b0,a1,na0), s04);
   And("dc", (b1,nb0,na1,a0), s05);
   And("dc", (b1,nb0,a1,a0), s06);
   And("dc", (b1,b0,na1,na0), s07);
   And("dc", (b1,b0,a1,na0), s08);
   
   Or("bd", (c1,c2,c3,c4,c5,c6), Carry);
   Or("cd", (s11,s12,s13,s14,s15,s16,s17,s18), s1);
   Or("dd", (s01,s02,s03,s04,s05,s06,s07,s08), s0);
   
}