/* D-flipflop (with a D-latch for comparison) */

#include "Sim.h"

void simnet()
{
   Signal set, reset, D, n_D, Clk, n_Clk;
   Signal slave_set, slave_reset;
   Sig( q, 1 );
   Sig( n_q, 1 );
   Sig( q1, 1 );
   Sig( n_q1, 1 );


   Switch ( "aa", D,   '0', Zero ); // Data
   Switch ( "da", Clk, '1', Zero);  // Write or "clock" signal

   /* ----------------------------------------------------
      Master stage
      ---------------------------------------------------- */
   Not("bc", D, n_D);

   And("ad", (D, Clk),   set);
   And("bd", (Clk, n_D), reset); 


   Nor ( "ae", (set,  q1),   n_q1);
   Nor ( "be", (n_q1,reset), q1);

   /* ----------------------------------------------------
      Slave stage
      ---------------------------------------------------- */
   Not("dg", Clk, n_Clk);

   And("ah", (q1, n_Clk), slave_set);  
   And("bh", (n_Clk, n_q1), slave_reset); 

   Nor("ai", (slave_set, q), n_q); 
   Nor("bi", (n_q, slave_reset), q); 

   Probe("bj", q);

   /* =================================================
      Compare to the D-latch
      ================================================= */
   Signal Xset, Xreset, XD, XClk, Xn_D;
   Sig( Xq0, 1 );
   Sig( Xn_q0, 1 );


   Switch ( "ea", XD,   '2', Zero );  // Data
   Switch ( "ga", XClk, '3', Zero );  // Write or "clock" signal

   Not("fc", XD, Xn_D);
   And("ed", (XD, XClk),   Xset);
   And("fd", (Xn_D, XClk), Xreset);

   Nor ( "ee", (Xset,  Xq0),   Xn_q0);
   Nor ( "fe", (Xn_q0,Xreset), Xq0);

   Probe ( "ff", Xq0 );      // 
}