/* Loop with D-latch */

#include "Sim.h"

void D_Latch(const SD &sd,
             const Signal &D, const Signal &Clk,
             const Signal &q, const Signal &n_q)
{
   Signal set, reset, n_D, n_Clk;

   Module( sd, "DLatch", (D, Clk), (n_q, q) );

   /* ----------------------------------------------------
      Master stage
      ---------------------------------------------------- */
   Not( SD(sd,"bc"), D, n_D);

   And( SD(sd,"ad"), (D, Clk),   set);
   And( SD(sd,"bd"), (Clk, n_D), reset);


   Nor ( SD(sd,"ae"), (set,  q),   n_q);
   Nor ( SD(sd,"be"), (n_q,reset), q);
}


void simnet()
{
   Sig(sw,1);
   Sig(out,1);
   Sig(clk,1);
   Signal q11, q12, n_q11;

   Switch("ba", sw,  '0', One);
   Switch("da", clk, '1', Zero);

   Not("bb", q11, n_q11);
   Or("bb", (sw,n_q11), out);
   D_Latch("bc", out, clk, q11, q12);
   Probe("ac", q11);

}