/* Loop with D-flipflop */

#include "Sim.h"

void D_Flipflop(const SD &sd, 
                const Signal &D, const Signal &Clk, 
                const Signal &q, const Signal &n_q)
{
   Signal set, reset, n_D, n_Clk;
   Signal slave_set, slave_reset;
   Sig( q1, 1 );
   Sig( n_q1, 1 );

   Module( sd, "Dff", (D, Clk), (q, n_q) ); 

   /* ----------------------------------------------------
      Master stage
      ---------------------------------------------------- */
   Not( SD(sd,"bc"), D, n_D);

   And( SD(sd,"ad"), (D, Clk),   set);
   And( SD(sd,"bd"), (Clk, n_D), reset); 


   Nor ( SD(sd,"ae"), (set,  q1),   n_q1);
   Nor ( SD(sd,"be"), (n_q1,reset), q1);

   /* ----------------------------------------------------
      Slave stage
      ---------------------------------------------------- */
   Not( SD(sd,"dg"), Clk, n_Clk);

   And( SD(sd,"ah"), (q1, n_Clk), slave_set);  
   And( SD(sd,"bh"), (n_Clk, n_q1), slave_reset); 

   Nor( SD(sd,"ai"), (slave_set, q), n_q); 
   Nor( SD(sd,"bi"), (n_q, slave_reset), q); 
}


void simnet()
{
   Sig(sw,1);
   Sig(out,1);
   Sig(clk,1);
   Signal q11, q12, n_q11;

   Switch("ba", sw,  '0', One);
   Switch("da", clk, '1', Zero);

   Not("bb", q11, n_q11);
   Or("bb", (sw,n_q11), out);
   D_Flipflop("bc", out, clk, q11, q12);
   Probe("ac", q11);

}