/* 6 registers making a 6-bit register  */

#include "Sim.h"

void D_Latch(const SD &coord,
               const Signal &D, const Signal &Clk, 
	       const Signal &q0, const Signal &n_q0)
{
   Module( coord, "D-latch", (D, Clk), (q0, n_q0));

   Signal n_D, set, reset;

   Not( SD(coord,"bc"), D, n_D);
   And( SD(coord,"ad"), (D, Clk),   set);
   And( SD(coord,"bd"), (n_D, Clk), reset);

   Nor( SD(coord,"ae"), (set,  q0),   n_q0);
   Nor( SD(coord,"be"), (reset,n_q0), q0);
}



void simnet()
{
   Signal clk;
   Signal q11, q12, q13, 
          q21, q22, q23,
	  q31, q32, q33,
	  q41, q42, q43,
	  q51, q52, q53,
	  q61, q62, q63;

   Switch("ba", clk, 'a', Zero);

   Switch("cb", q11, '5', Zero);
   D_Latch("bb", q11, clk, q12, q13);   // q13 is q-bar
   Probe("ab", q12);

   Switch("cc", q21, '4', Zero);
   D_Latch("bc", q21, clk, q22, q23);
   Probe("ac", q22);

   Switch("cd", q31, '3', Zero);
   D_Latch("bd", q31, clk, q32, q33);
   Probe("ad", q32);

   Switch("ce", q41, '2', Zero);
   D_Latch("be", q41, clk, q42, q43);
   Probe("ae", q42);

   Switch("cf", q51, '1', Zero);
   D_Latch("bf", q51, clk, q52, q53);
   Probe("af", q52);

   Switch("cg", q61, '0', Zero);
   D_Latch("bg", q61, clk, q62, q63);
   Probe("ag", q62);
}