/* Cascading D-flipflop --- shift register */

#include "Sim.h"

void D_Flipflop(const SD &sd, 
                const Signal &D, const Signal &Clk, 
                const Signal &q, const Signal &n_q)
{
   Signal set, reset, n_D, n_Clk;
   Signal slave_set, slave_reset;
   Sig( q1, 1 );
   Sig( n_q1, 1 );

   Module( sd, "Dff", (D, Clk), (q, n_q) ); 

   /* ----------------------------------------------------
      Master stage
      ---------------------------------------------------- */
   Not( SD(sd,"bc"), D, n_D);

   And( SD(sd,"ad"), (D, Clk),   set);
   And( SD(sd,"bd"), (Clk, n_D), reset); 


   Nor ( SD(sd,"ae"), (set,  q1),   n_q1);
   Nor ( SD(sd,"be"), (n_q1,reset), q1);

   /* ----------------------------------------------------
      Slave stage
      ---------------------------------------------------- */
   Not( SD(sd,"dg"), Clk, n_Clk);

   And( SD(sd,"ah"), (q1, n_Clk), slave_set);  
   And( SD(sd,"bh"), (n_Clk, n_q1), slave_reset); 

   Nor( SD(sd,"ai"), (slave_set, q), n_q); 
   Nor( SD(sd,"bi"), (n_q, slave_reset), q); 
}


void simnet()
{
   Signal sw_1, sw_2;
   Signal q11, q12, q21, q22, q31, q32, q41, q42, q51, q52, q61, q62;

   Switch("ba", sw_1, '0', Zero);
   Switch("da", sw_2, '1', Zero);

   D_Flipflop("bb", sw_1, sw_2, q11, q12);
   Probe("ab", q11);

   D_Flipflop("bc", q11,  sw_2, q21, q22);
   Probe("ac", q21);

   D_Flipflop("bd", q21,  sw_2, q31, q32);
   Probe("ad", q31);

   D_Flipflop("be", q31,  sw_2, q41, q42);
   Probe("ae", q41);

   D_Flipflop("bf", q41,  sw_2, q51, q52);
   Probe("af", q51);

   D_Flipflop("bg", q51,  sw_2, q61, q62);
   Probe("ag", q61);
}