#include "Sim.h"
void Full_Adder (const SD &coord, const Signal &CarryIn, const Signal &a, const Signal &b, const Signal &CarryOut, const Signal &Sum);

void One_Bit_ALU (const SD &coord, const Signal &a, const Signal &b, const Signal &c_in, const Signal &s, const Signal &z, const Signal &c_out);

void Full_Adder (const SD &coord, const Signal &CarryIn, const Signal &a, const Signal &b, const Signal &CarryOut, const Signal &Sum)
{
	Module( coord, "Full_Adder", (CarryIn, a, b), (CarryOut, Sum) );
	Signal x(1, "x");
	Signal y(1, "y");
	Signal z(1, "z");
	Xor ( SD(coord, "aa"), (a, b), x);
	Xor ( SD(coord, "ab"), (x, CarryIn), Sum);
	And ( SD(coord, "bb"), (a, b), y);
	And ( SD(coord, "cb"), (CarryIn, x), z);
	Or ( SD(coord, "bc-cc"), (y, z), CarryOut);
}
void One_Bit_ALU (const SD &coord, const Signal &a, const Signal &b, const Signal &c_in, const Signal &s, const Signal &z, const Signal &c_out)
{
	Module( coord, "One_Bit_ALU", (a, b, c_in, s), (z, c_out) );
	Signal Out_Sum(1, "Out_Sum");
	Signal Out_Not(1, "Out_Not");
	Signal Out_And(1, "Out_And");
	Signal Out_Or(1, "Out_Or");
	Full_Adder( SD(coord, "aa"), (a), (b), (c_in), (c_out), (Out_Sum));
	Not ( SD(coord, "aa"), a, Out_Not);
	And ( SD(coord, "aa"), (a, b), Out_And);
	Or ( SD(coord, "aa"), (a, b), Out_Or);
	Mux ( SD(coord, "ab"), (s[1], s[0]), ((Out_Or), (Out_And), (Out_Not), (Out_Sum)), z);
}
int simnet()
{
	Signal c(1, "c");
	Signal a(1, "a");
	Signal b(1, "b");
	Signal y(1, "y");
	Signal x(1, "x");
	Signal z(1, "z");
	Signal c_out(1, "c_out");
	Switch ("1a", c, 'c', Zero);
	Switch ("3a", a, 'a', Zero);
	Switch ("4a", b, 'b', Zero);
	Switch ("6a", y, '1', Zero);
	Switch ("7a", x, '0', Zero);
	One_Bit_ALU("2b-5b", (a), (b), (c), (y, x), (z), (c_out));
	Probe ("3c", z);
	Probe ("1c", c_out);
}