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Design of the Advanced Pipelined CPU in Logic-SIM

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• Overview
  • The Advanced Pipelined CPU is built on the Basic Pipelined CPU using a number of forwarding circuits.

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• How to implement the Advanced Pipelined CPU:

  • You need 2 forwarding registers (with tags)

  • You need a number of "forwarding circuits"

  • And you need to modify some of the existing circuits (trivial changes)

  • The following figure gives the circuit diagram on the advanced pipeline.

    The changes (components and connections) that need to be made in the basic pipeline has been highlighted using the magenta color.

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  • Here's a list of the changes that need to be made:
    1. Add data forwarding registers

    2. Add data forwarding circuits (smart muxes)

    3. Move the branch executing hardware from the MEM stage into the ID stage (delete some circuits from the MEM stage and add some circuits in the ID stage)

    4. Change some stall circuits.

  • Below, I describe the changes in each component individually in more details.

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• The IF Stage
  • Unchanged

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• The ID Stage
  • The execution of the branch instruction is moved forwarded into the ID stage.

    I will highlight the changes in magenta.

  • Schematics:

  • Macro Definition:

    Define ID clk IR_ID[15..0] PC[15..0] src1[15..0] src2[15..0] src3[15..0] | src1_sel[0..3] src2_sel[0..3] src3_sel[0..3] PC1[15..0] A[15..0] B[15..0] IR_Const[15..0] D[15..0] bcc1 bcc0 BraDest[15..0]; ..... Endef;

  • New input signals:
    • None

  • New Output signals:
    • bcc1, bcc0: branch condition bits from instruction (bcc1 = bit 8, bcc0 = bit 7)
    • BraDest[15..0]: Destination address.

  • New Operation:
    • Add the constant to to PC[15..0] and set the result out as BraDest[15..0] (for branching purposes)
    • Send the Condition Code bits in the instruction out as "bcc1" and "bcc0" (The BranchDecision circuit - click here ) will take care of the branching itself)

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• The EX Stage
  • Unchanged

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• The MEM Stage
  • The branching is moved forwards to the ID stage, so we can remove the branch-condition codes from this stage.

  • But... you don't really need to; as long as you RENAME the "bcc1" and "bcc0" output of the MEM circuit so that they do not coincide with the "bcc1" and "bcc0" output of the ID stage

  • But for safety (Parkinson's law :-)), it's best to define a new MEM stage circuit:

  • Macro Definition:

    Define MEM clk IR_MEM[15..0] src1[15..0] src2[15..0] src3[15..0] | MemRq Read ALUout[15..0] DMAR[15..0] SMDR[15..0]; ..... Endef;

    Just delete the circuits that makes the "bcc1" and "bcc0" signals from the "Basic Pipe MEM stage" circuit.

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• The WR Stage
  • Unchanged

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• The PSR
  • Unchanged

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• The Registers
  • Unchanged

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• The Branch Decision Circuit D
  • Unchanged

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• The Stall_IF circuit
  • Unchanged

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• The Stall_ID circuit
  • Unchanged

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• The Stall_EX circuit
  • Macro Definition:

    Define Stall_EX MEM_Stall IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] | stall ; .... Endef;

  • Input signals:
    • MEM_Stall = Stall signal from MEM stage.
    • IR_ID[15..0] = instruction in ID stage
    • IR_EX[15..0] = instruction in EX stage
    • IR_MEM[15..0] = instruction in MEM stage

  • Output signals:
    • stall = 0, no stall
    • stall = 1, stall

  • Operation:
    • Set stall output to ONE when:

      (IR_MEM.LoadBit == 1) AND (IR_EX.BranchBit == 0) AND ( IR_EX.Src1 == IR_MEM.Dest OR IR_EX.Src2 == IR_MEM.Dest )

    The reason why is given in this webpage: click here

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• The Stall_MEM circuit
  • Unchanged

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  Data Forwarding Hardware

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• Data forwarding registers
  • Schematics:

  • Macro Definition:

    Define DataForwRegs clk RegID[2..0] ALUout[15..0] | Tag1[2..0] Value1[15..0] Tag2[2..0] Value2[15..0]; .... Endef;

  • NOTE: the value Value1[15..0] is the most recent value.

• General Purpose Data forwarding circuit
  • Usage:
    General purpose data forwarding circuit.

    Use a number of these to build up the actual data forwarding circuits

  • Schematics:

  • Macro Definition:

    Define GP_DataForwCircuit RegID[2..0] Tag[2..0] Value[15..0] In[15..0] | Out[15..0]; .... Endef;

  • Operation:
    • If RegID[2..0] == Tag[2..0], then Out[15..0] is equal to Value[15..0]

    • Otherwise, Out[15..0] is equal to In[15..0]

• Using Data forwarding circuit to obtain src1 operand
  • Schematics:

• Using Data forwarding circuit to obtain src2 operand
  • Schematics:

• NOTE
  • You can probably best make the following macro first:

    This circuit consists of the circuit inside the yellow boundary:

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• The AdvPipe circuit
  • Schematics:

  • Macro Definition:

    Define AdvPipe clk reset DatabusIn[15..0] | PC[15..0] N Z branch MemRq Read AddrBusOut[15..0] DataBusOut[15..0] Stall_IF Stall_ID Stall_EX Stall_MEM IR_ID[15..0] IR_EX[15..0] IR_MEM[15..0] IR_WR[15..0] Reg0[15..0] Reg1[15..0] Reg2[15..0] Reg3[15..0] Reg4[15..0] Reg5[15..0] Reg6[15..0] Reg7[15..0] IF_PC[15..0] IF_IF_Out[15..0] ID_PC1[15..0] ID_A[15..0] ID_B[15..0] ID_Const[15..0] ID_D[15..0] EX_Op1[15..0] EX_Op2[15..0] EX_ALUout[15..0] EX_DMAR[15..0] EX_SMDR[15..0] MEM_ALUout[15..0] MEM_LMDR[15..0] WR_C_Enable WR_RegSel[2..0] WR_CBus[15..0] Endef;

  • Input signals:
    • clk = clock
    • reset = reset signal (set PC to 0)
    • DatabusIn[15..0] = data from Databus

  • Output signals:
    • PC[15..0] = Value of PC (in IF stage)
    • N = N flag (from PSR)
    • Z = Z flag (from PSR)
    • branch = branch decision (from Branch Decision Circuit D)

    • MemRq = Memory Request (OR result of MemRq from IF stage and MemRq from MEM stage)
    • READ = Read (OR result of Read from IF stage and Read from MEM stage)
    • AddrBusOut[15..0] = addres value (each bit AddrBusOut[i] is the OR result of AddrBusOut[i] from IF stage and AddrBusOut[i] from MEM stage)
    • DataBusOut[15..0] = addres value (each bit DataBusOut[i] is the OR result of DataBusOut[i] from IF stage and DataBusOut[i] from MEM stage)

    • Stall_IF, Stall_ID, Stall_EX, Stall_MEM = Stall indicators (outputs of the Stall Circuits)
    • IR_ID[15..0], IR_EX[15..0], IR_MEM[15..0], IR_WR[15..0] = values in the instruction registers in the ID, EX, MEM and WR stages. (These are the outputs of 16 bit Dffs of the 4 Instruction registers)

    • Reg0[15..0], Reg1[15..0], ..., Reg8[15..0] = registers

    • IF_PC[15..0] = Output of the IF stage: the PC output
    • IF_IF_Out[15..0] = Output of the IF stage: the IF_IF_Out output

    • ID_PC1[15..0] = Output of the ID stage: the PC1 output
    • ID_A[15..0] = Output of the ID stage: the A output
    • ID_B[15..0] = Output of the ID stage: the B output
    • ID_Const[15..0] = Output of the ID stage: the IR_Const output
    • ID_D[15..0] = Output of the ID stage: the D output

    • EX_Op1[15..0] = Output of the pre-EX stage multiplexor: Operand 1
    • EX_Op2[15..0] = Output of the pre-EX stage multiplexor: Operand 2

    • EX_ALUout[15..0] = Output of the EX stage: the ALUout output
    • EX_DMAR[15..0] = Output of the EX stage: the DMAR output
    • EX_SMDR[15..0] = Output of the EX stage: the SMDR output

    • MEM_ALUout[15..0] = Output of the ME stage: the ALUout output
    • MEM_LMDR[15..0] = Output of the ME stage: the LMDR output

    • WR_C_Enable = C_Enabled signal (write register)
    • WR_RegSel[2..0] = Register select (one of 8)
    • WR_CBus[15..0]

  • Operation:
    • If wired correctly, I hope the CPU will work (if I did not make any design error :-))